Lines Matching +full:0 +full:x1ff
47 #define AQ_HW_FW_SM_RAM 0x2U
48 #define AQ_CFG_FW_MIN_VER_EXPECTED 0x01050006U
53 return (0); in aq_hw_err_from_flags()
58 u32 chip_features = 0U; in aq_hw_chip_features_init()
60 u32 mif_rev = val & 0xFFU; in aq_hw_chip_features_init()
62 if ((0xFU & mif_rev) == 1U) { in aq_hw_chip_features_init()
66 } else if ((0xFU & mif_rev) == 2U) { in aq_hw_chip_features_init()
72 } else if ((0xFU & mif_rev) == 0xAU) { in aq_hw_chip_features_init()
85 int err = 0; in aq_hw_fw_downld_dwords()
92 if (err < 0) { in aq_hw_fw_downld_dwords()
139 int err = 0; in aq_hw_init_ucp()
142 hw->fw_version.raw = 0; in aq_hw_init_ucp()
152 if (err < 0) { in aq_hw_init_ucp()
158 if (!AQ_READ_REG(hw, 0x370)) { in aq_hw_init_ucp()
159 unsigned int rnd = 0; in aq_hw_init_ucp()
160 unsigned int ucp_0x370 = 0; in aq_hw_init_ucp()
164 ucp_0x370 = 0x02020202 | (0xFEFEFEFE & rnd); in aq_hw_init_ucp()
168 reg_glb_cpu_scratch_scp_set(hw, 0, 25); in aq_hw_init_ucp()
172 AQ_HW_WAIT_FOR((hw->mbox_addr = AQ_READ_REG(hw, 0x360)) != 0, 400U, 20); in aq_hw_init_ucp()
185 int err = 0; in aq_hw_mpi_create()
189 if (err < 0) in aq_hw_mpi_create()
199 int err = 0; in aq_hw_mpi_read_stats()
257 if (err < 0) { in aq_hw_get_link_state()
262 *link_speed = 0; in aq_hw_get_link_state()
264 return (0); in aq_hw_get_link_state()
288 *link_speed = 0U; in aq_hw_get_link_state()
295 // AQ_DBG_EXIT(0); in aq_hw_get_link_state()
296 return (0); in aq_hw_get_link_state()
308 if ((mac[0] & 1) || ((mac[0] | mac[1] | mac[2]) == 0)) { in aq_hw_get_mac_permanent()
310 u32 h = 0; in aq_hw_get_mac_permanent()
311 u32 l = 0; in aq_hw_get_mac_permanent()
313 …printf("atlantic: HW MAC address %x:%x:%x:%x:%x:%x is multicast or empty MAC", mac[0], mac[1], mac… in aq_hw_get_mac_permanent()
319 l = 0xE3000000U in aq_hw_get_mac_permanent()
320 | (0xFFFFU & rnd) in aq_hw_get_mac_permanent()
321 | (0x00 << 16); in aq_hw_get_mac_permanent()
322 h = 0x8001300EU; in aq_hw_get_mac_permanent()
324 mac[5] = (u8)(0xFFU & l); in aq_hw_get_mac_permanent()
326 mac[4] = (u8)(0xFFU & l); in aq_hw_get_mac_permanent()
328 mac[3] = (u8)(0xFFU & l); in aq_hw_get_mac_permanent()
330 mac[2] = (u8)(0xFFU & l); in aq_hw_get_mac_permanent()
331 mac[1] = (u8)(0xFFU & h); in aq_hw_get_mac_permanent()
333 mac[0] = (u8)(0xFFU & h); in aq_hw_get_mac_permanent()
345 aq_hw_mpi_set(hw, MPI_DEINIT, 0); in aq_hw_deinit()
346 AQ_DBG_EXIT(0); in aq_hw_deinit()
347 return (0); in aq_hw_deinit()
353 aq_hw_mpi_set(hw, MPI_POWER, 0); in aq_hw_set_power()
354 AQ_DBG_EXIT(0); in aq_hw_set_power()
355 return (0); in aq_hw_set_power()
363 int err = 0; in aq_hw_reset()
368 if (err < 0) in aq_hw_reset()
371 itr_irq_reg_res_dis_set(hw, 0); in aq_hw_reset()
375 AQ_HW_WAIT_FOR(itr_res_irq_get(hw) == 0, 1000, 10); in aq_hw_reset()
376 if (err < 0) { in aq_hw_reset()
393 u32 tc = 0U; in aq_hw_qos_set()
394 u32 buff_size = 0U; in aq_hw_qos_set()
395 unsigned int i_priority = 0U; in aq_hw_qos_set()
396 int err = 0; in aq_hw_qos_set()
400 tps_tx_pkt_shed_desc_rate_curr_time_res_set(hw, 0x0U); in aq_hw_qos_set()
401 tps_tx_pkt_shed_desc_rate_lim_set(hw, 0xA); in aq_hw_qos_set()
404 tps_tx_pkt_shed_desc_vm_arb_mode_set(hw, 0U); in aq_hw_qos_set()
407 tps_tx_pkt_shed_desc_tc_arb_mode_set(hw, 0U); in aq_hw_qos_set()
408 tps_tx_pkt_shed_data_arb_mode_set(hw, 0U); in aq_hw_qos_set()
410 tps_tx_pkt_shed_tc_data_max_credit_set(hw, 0xFFF, 0U); in aq_hw_qos_set()
411 tps_tx_pkt_shed_tc_data_weight_set(hw, 0x64, 0U); in aq_hw_qos_set()
412 tps_tx_pkt_shed_desc_tc_max_credit_set(hw, 0x50, 0U); in aq_hw_qos_set()
413 tps_tx_pkt_shed_desc_tc_weight_set(hw, 0x1E, 0U); in aq_hw_qos_set()
427 tc = 0; in aq_hw_qos_set()
442 rpf_rpb_user_priority_tc_map_set(hw, i_priority, 0U); in aq_hw_qos_set()
451 int err = 0; in aq_hw_offload_set()
457 if (err < 0) in aq_hw_offload_set()
463 if (err < 0) in aq_hw_offload_set()
467 tdm_large_send_offload_en_set(hw, 0xFFFFFFFFU); in aq_hw_offload_set()
468 if (err < 0) in aq_hw_offload_set()
473 u32 i = 0; in aq_hw_offload_set()
474 u32 val = (8U < HW_ATL_B0_LRO_RXD_MAX) ? 0x3U : in aq_hw_offload_set()
475 ((4U < HW_ATL_B0_LRO_RXD_MAX) ? 0x2U : in aq_hw_offload_set()
476 ((2U < HW_ATL_B0_LRO_RXD_MAX) ? 0x1U : 0x0)); in aq_hw_offload_set()
478 for (i = 0; i < HW_ATL_B0_RINGS_MAX; i++) in aq_hw_offload_set()
481 rpo_lro_time_base_divider_set(hw, 0x61AU); in aq_hw_offload_set()
482 rpo_lro_inactive_interval_set(hw, 0); in aq_hw_offload_set()
483 /* the LRO timebase divider is 5 uS (0x61a), in aq_hw_offload_set()
485 * we need to multiply by 50(0x32) to get in aq_hw_offload_set()
494 rpo_lro_patch_optimization_en_set(hw, 0U); in aq_hw_offload_set()
500 rpo_lro_en_set(hw, (hw->lro_enabled ? 0xFFFFFFFFU : 0U)); in aq_hw_offload_set()
513 int err = 0; in aq_hw_init_tx_path()
520 thm_lso_tcp_flag_of_first_pkt_set(hw, 0x0FF6U); in aq_hw_init_tx_path()
521 thm_lso_tcp_flag_of_middle_pkt_set(hw, 0x0FF6U); in aq_hw_init_tx_path()
522 thm_lso_tcp_flag_of_last_pkt_set(hw, 0x0F7FU); in aq_hw_init_tx_path()
528 AQ_WRITE_REG(hw, 0x00007040U, 0x00010000U);//IS_CHIP_FEATURE(TPO2) ? 0x00010000U : 0x00000000U); in aq_hw_init_tx_path()
529 tdm_tx_dca_en_set(hw, 0U); in aq_hw_init_tx_path()
530 tdm_tx_dca_mode_set(hw, 0U); in aq_hw_init_tx_path()
542 unsigned int control_reg_val = 0U; in aq_hw_init_rx_path()
554 reg_rx_flr_rss_control1set(hw, 0xB3333333U); in aq_hw_init_rx_path()
558 rpfl2_uc_flr_en_set(hw, (i == 0U) ? 1U : 0U, i); in aq_hw_init_rx_path()
562 reg_rx_flr_mcst_flr_msk_set(hw, 0x00000000U); in aq_hw_init_rx_path()
563 reg_rx_flr_mcst_flr_set(hw, 0x00010FFFU, 0U); in aq_hw_init_rx_path()
566 rpf_vlan_outer_etht_set(hw, 0x88A8U); in aq_hw_init_rx_path()
567 rpf_vlan_inner_etht_set(hw, 0x8100U); in aq_hw_init_rx_path()
577 control_reg_val = 0x000F0000U; //RPF2 in aq_hw_init_rx_path()
580 control_reg_val |= 0x1EU; in aq_hw_init_rx_path()
582 AQ_WRITE_REG(hw, 0x00005040U, control_reg_val); in aq_hw_init_rx_path()
586 rpfl2broadcast_count_threshold_set(hw, 0xFFFFU & (~0U / 256U)); in aq_hw_init_rx_path()
588 rdm_rx_dca_en_set(hw, 0U); in aq_hw_init_rx_path()
589 rdm_rx_dca_mode_set(hw, 0U); in aq_hw_init_rx_path()
598 int err = 0; in aq_hw_mac_addr_set()
599 unsigned int h = 0U; in aq_hw_mac_addr_set()
600 unsigned int l = 0U; in aq_hw_mac_addr_set()
607 h = (mac_addr[0] << 8) | (mac_addr[1]); in aq_hw_mac_addr_set()
611 rpfl2_uc_flr_en_set(hw, 0U, index); in aq_hw_mac_addr_set()
626 int err = 0; in aq_hw_init()
627 u32 val = 0; in aq_hw_init()
633 AQ_WRITE_REG(hw, AQ_HW_PCI_REG_CONTROL_6_ADR, (val & ~0x707) | 0x404); in aq_hw_init()
651 if (err < 0) in aq_hw_init()
656 itr_irq_status_cor_en_set(hw, 0); //Disable clear-on-read for status in aq_hw_init()
659 itr_irq_mode_set(hw, 0x6); //MSIX + multi vector in aq_hw_init()
661 itr_irq_mode_set(hw, 0x5); //MSI + multi vector in aq_hw_init()
663 reg_gen_irq_map_set(hw, 0x80 | adm_irq, 3); in aq_hw_init()
689 {80, 120},//{0x6U, 0x38U},/* 10Gbit */ in aq_hw_interrupt_moderation_set()
690 {0xCU, 0x70U},/* 5Gbit */ in aq_hw_interrupt_moderation_set()
691 {0xCU, 0x70U},/* 5Gbit 5GS */ in aq_hw_interrupt_moderation_set()
692 {0x18U, 0xE0U},/* 2.5Gbit */ in aq_hw_interrupt_moderation_set()
693 {0x30U, 0x80U},/* 1Gbit */ in aq_hw_interrupt_moderation_set()
694 {0x4U, 0x50U},/* 100Mbit */ in aq_hw_interrupt_moderation_set()
697 {0x4fU, 0x1ff},//{0xffU, 0xffU}, /* 10Gbit */ in aq_hw_interrupt_moderation_set()
698 {0x4fU, 0xffU}, /* 5Gbit */ in aq_hw_interrupt_moderation_set()
699 {0x4fU, 0xffU}, /* 5Gbit 5GS */ in aq_hw_interrupt_moderation_set()
700 {0x4fU, 0xffU}, /* 2.5Gbit */ in aq_hw_interrupt_moderation_set()
701 {0x4fU, 0xffU}, /* 1Gbit */ in aq_hw_interrupt_moderation_set()
702 {0x4fU, 0xffU}, /* 100Mbit */ in aq_hw_interrupt_moderation_set()
705 u32 speed_index = 0U; //itr settings for 10 g in aq_hw_interrupt_moderation_set()
709 int active = custom_itr != 0; in aq_hw_interrupt_moderation_set()
716 itr_rx |= AQ_HW_NIC_timers_table_rx_[speed_index][0] << 0x8U; /* set min timer value */ in aq_hw_interrupt_moderation_set()
717 itr_rx |= AQ_HW_NIC_timers_table_rx_[speed_index][1] << 0x10U; /* set max timer value */ in aq_hw_interrupt_moderation_set()
719 itr_tx |= AQ_HW_NIC_timers_table_tx_[speed_index][0] << 0x8U; /* set min timer value */ in aq_hw_interrupt_moderation_set()
720 itr_tx |= AQ_HW_NIC_timers_table_tx_[speed_index][1] << 0x10U; /* set max timer value */ in aq_hw_interrupt_moderation_set()
722 if (custom_itr > 0x1FF) in aq_hw_interrupt_moderation_set()
723 custom_itr = 0x1FF; in aq_hw_interrupt_moderation_set()
725 itr_rx |= (custom_itr/2) << 0x8U; /* set min timer value */ in aq_hw_interrupt_moderation_set()
726 itr_rx |= custom_itr << 0x10U; /* set max timer value */ in aq_hw_interrupt_moderation_set()
728 itr_tx |= (custom_itr/2) << 0x8U; /* set min timer value */ in aq_hw_interrupt_moderation_set()
729 itr_tx |= custom_itr << 0x10U; /* set max timer value */ in aq_hw_interrupt_moderation_set()
755 * @return 0 - OK, <0 - error
762 for (i = 0; i < AQ_HW_VLAN_MAX_FILTERS; i++) { in hw_atl_b0_hw_vlan_set()
763 hw_atl_rpf_vlan_flr_en_set(self, 0U, i); in hw_atl_b0_hw_vlan_set()
764 hw_atl_rpf_vlan_rxq_en_flr_set(self, 0U, i); in hw_atl_b0_hw_vlan_set()
771 if (aq_vlans[i].queue != 0xFF) { in hw_atl_b0_hw_vlan_set()
799 rpfl2multicast_flr_en_set(self, mc_promisc, 0); in aq_hw_set_promisc()
801 AQ_DBG_EXIT(0); in aq_hw_set_promisc()
807 u32 addr = 0U; in aq_hw_rss_hash_set()
808 u32 i = 0U; in aq_hw_rss_hash_set()
809 int err = 0; in aq_hw_rss_hash_set()
815 for (i = 10, addr = 0U; i--; ++addr) { in aq_hw_rss_hash_set()
820 AQ_HW_WAIT_FOR(rpf_rss_key_wr_en_get(self) == 0, in aq_hw_rss_hash_set()
822 if (err < 0) in aq_hw_rss_hash_set()
836 u32 addr = 0U; in aq_hw_rss_hash_get()
837 u32 i = 0U; in aq_hw_rss_hash_get()
838 int err = 0; in aq_hw_rss_hash_get()
842 for (i = 10, addr = 0U; i--; ++addr) { in aq_hw_rss_hash_get()
858 int err = 0; in aq_hw_rss_set()
859 u32 i = 0U; in aq_hw_rss_set()
861 memset(bitary, 0, sizeof(bitary)); in aq_hw_rss_set()
865 ((rss_table[i]) << ((i * 3U) & 0xFU)); in aq_hw_rss_set()
872 AQ_HW_WAIT_FOR(rpf_rss_redir_wr_en_get(self) == 0, in aq_hw_rss_set()
874 if (err < 0) in aq_hw_rss_set()
886 int err = 0; in aq_hw_udp_rss_enable()
889 * Disable RSS for UDP using rx flow filter 0. in aq_hw_udp_rss_enable()
891 * 0x5040 control reg does not work. in aq_hw_udp_rss_enable()
893 hw_atl_rpf_l3_l4_enf_set(self, true, 0); in aq_hw_udp_rss_enable()
894 hw_atl_rpf_l4_protf_en_set(self, true, 0); in aq_hw_udp_rss_enable()
895 hw_atl_rpf_l3_l4_rxqf_en_set(self, true, 0); in aq_hw_udp_rss_enable()
896 hw_atl_rpf_l3_l4_actf_set(self, L2_FILTER_ACTION_HOST, 0); in aq_hw_udp_rss_enable()
897 hw_atl_rpf_l3_l4_rxqf_set(self, 0, 0); in aq_hw_udp_rss_enable()
898 hw_atl_rpf_l4_protf_set(self, HW_ATL_RX_UDP, 0); in aq_hw_udp_rss_enable()
900 hw_atl_rpf_l3_l4_enf_set(self, false, 0); in aq_hw_udp_rss_enable()