Lines Matching +full:0 +full:x12440000
18 #size-cells = <0>;
20 U74_0: cpu@0 {
22 reg = <0>;
118 #clock-cells = <0>;
120 clock-frequency = <0>;
125 #clock-cells = <0>;
127 clock-frequency = <0>;
132 #clock-cells = <0>;
134 clock-frequency = <0>;
139 #clock-cells = <0>;
141 clock-frequency = <0>;
154 reg = <0x0 0x2000000 0x0 0x10000>;
161 reg = <0x0 0x2010000 0x0 0x1000>;
171 compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0";
172 reg = <0x0 0xc000000 0x0 0x4000000>;
176 #address-cells = <0>;
183 reg = <0x0 0x10000000 0x0 0x10000>;
188 data-addr = <0>;
196 reg = <0x0 0x10010000 0x0 0x10000>;
201 data-addr = <0>;
209 reg = <0x0 0x11800000 0x0 0x10000>;
217 reg = <0x0 0x11840000 0x0 0x10000>;
223 reg = <0x0 0x118b0000 0x0 0x10000>;
230 #size-cells = <0>;
236 reg = <0x0 0x118c0000 0x0 0x10000>;
243 #size-cells = <0>;
249 reg = <0x0 0x11910000 0x0 0x10000>,
250 <0x0 0x11858000 0x0 0x1000>;
263 reg = <0x0 0x12430000 0x0 0x10000>;
276 reg = <0x0 0x12440000 0x0 0x10000>;
289 reg = <0x0 0x12450000 0x0 0x10000>;
296 #size-cells = <0>;
302 reg = <0x0 0x12460000 0x0 0x10000>;
309 #size-cells = <0>;
315 reg = <0x0 0x12480000 0x0 0x10000>;
325 reg = <0x0 0x124a0000 0x0 0x10000>;
332 #thermal-sensor-cells = <0>;