Lines Matching +full:0 +full:x10021000
24 #size-cells = <0>;
25 cpu0: cpu@0 {
32 reg = <0x0>;
59 reg = <0x1>;
86 reg = <0x2>;
113 reg = <0x3>;
140 reg = <0x4>;
184 #address-cells = <0>;
185 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
186 reg = <0x0 0xc000000 0x0 0x4000000>;
190 <&cpu0_intc 0xffffffff>,
191 <&cpu1_intc 0xffffffff>, <&cpu1_intc 9>,
192 <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>,
193 <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>,
194 <&cpu4_intc 0xffffffff>, <&cpu4_intc 9>;
198 reg = <0x0 0x10000000 0x0 0x1000>;
205 reg = <0x0 0x10010000 0x0 0x1000>;
213 reg = <0x0 0x10011000 0x0 0x1000>;
221 reg = <0x0 0x10030000 0x0 0x1000>;
228 #size-cells = <0>;
233 reg = <0x0 0x10031000 0x0 0x1000>;
240 #size-cells = <0>;
245 reg = <0x0 0x10040000 0x0 0x1000>,
246 <0x0 0x20000000 0x0 0x10000000>;
251 #size-cells = <0>;
256 reg = <0x0 0x10041000 0x0 0x1000>,
257 <0x0 0x30000000 0x0 0x10000000>;
262 #size-cells = <0>;
267 reg = <0x0 0x10050000 0x0 0x1000>;
272 #size-cells = <0>;
279 reg = <0x0 0x10090000 0x0 0x2000>,
280 <0x0 0x100a0000 0x0 0x1000>;
286 #size-cells = <0>;
291 reg = <0x0 0x10020000 0x0 0x1000>;
300 reg = <0x0 0x10021000 0x0 0x1000>;
316 reg = <0x0 0x2010000 0x0 0x1000>;
324 reg = <0x0 0x10060000 0x0 0x1000>;
337 reg = <0xe 0x00000000 0x0 0x80000000>,
338 <0xd 0xf0000000 0x0 0x10000000>,
339 <0x0 0x100d0000 0x0 0x1000>;
343 bus-range = <0x0 0xff>;
344 ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000>, /* I/O */
345 <0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000>, /* mem */
346 <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x10000000>, /* mem */
347 <0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>; /* mem prefetchable */
348 num-lanes = <0x8>;
352 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
353 interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>,
354 <0x0 0x0 0x0 0x2 &plic0 58>,
355 <0x0 0x0 0x0 0x3 &plic0 59>,
356 <0x0 0x0 0x0 0x4 &plic0 60>;
359 pwren-gpios = <&gpio 5 0>;
360 reset-gpios = <&gpio 8 0>;