Lines Matching +full:0 +full:xfe200000
68 size = <0 0x1000000>;
69 alignment = <0 0x1000000>;
72 size = <0 0x400000>;
73 alignment = <0 0x400000>;
76 size = <0 0x2000000>;
77 alignment = <0 0x2000000>;
82 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
86 ranges = <0x0 0xf 0xf4000000 0x200000>;
90 ranges = <0x0 0xf 0xf4200000 0x200000>;
94 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
95 reg = <0xf 0xfe000000 0 0x00001000>;
98 flash@0 {
102 reg = <0>;
106 reg = <0x00000000 0x00100000>;
111 reg = <0x00100000 0x00500000>;
116 reg = <0x00600000 0x00100000>;
121 reg = <0x00700000 0x00900000>;
129 reg = <0x51>;
133 reg = <0x52>;
137 reg = <0x68>;
138 interrupts = <0x1 0x1 0 0>;
142 reg = <0x4c>;
149 reg = <0x21>;
153 reg = <0x22>;
157 reg = <0x23>;
161 reg = <0x24>;
165 reg = <0x50>;
169 reg = <0x55>;
173 reg = <0x56>;
177 reg = <0x57>;
182 /* 0x6E: ICS9FG108 */
250 reg = <0xf 0xfe0c0000 0 0x11000>;
253 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
256 ranges = <0 0 0xc 0x30000000 0 0x10000000>;
261 reg = <0xf 0xfe124000 0 0x1000>;
262 ranges = <0 0 0xf 0xe8000000 0x08000000
263 3 0 0xf 0xffdf0000 0x00008000>;
265 flash@0,0 {
267 reg = <0 0 0x08000000>;
272 board-control@3,0 {
274 reg = <3 0 0x30>;
279 reg = <0xf 0xfe200000 0 0x1000>;
280 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
281 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
282 pcie@0 {
283 ranges = <0x02000000 0 0xe0000000
284 0x02000000 0 0xe0000000
285 0 0x20000000
287 0x01000000 0 0x00000000
288 0x01000000 0 0x00000000
289 0 0x00010000>;
294 reg = <0xf 0xfe201000 0 0x1000>;
295 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
296 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
297 pcie@0 {
298 ranges = <0x02000000 0 0xe0000000
299 0x02000000 0 0xe0000000
300 0 0x20000000
302 0x01000000 0 0x00000000
303 0x01000000 0 0x00000000
304 0 0x00010000>;
309 reg = <0xf 0xfe202000 0 0x1000>;
310 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
311 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
312 pcie@0 {
313 ranges = <0x02000000 0 0xe0000000
314 0x02000000 0 0xe0000000
315 0 0x20000000
317 0x01000000 0 0x00000000
318 0x01000000 0 0x00000000
319 0 0x00010000>;
325 #size-cells = <0>;
328 gpios = <&gpio0 1 0>, <&gpio0 0 0>;
330 p4080mdio0: mdio@0 {
332 #size-cells = <0>;
333 reg = <0>;
335 phyrgmii: ethernet-phy@0 {
336 reg = <0x0>;
342 #size-cells = <0>;
346 reg = <0x1c>;
350 reg = <0x1d>;
354 reg = <0x1e>;
358 reg = <0x1f>;
364 #size-cells = <0>;
369 reg = <0x1c>;
373 reg = <0x1d>;
377 reg = <0x1e>;
381 reg = <0x1f>;
387 #size-cells = <0>;
391 reg = <0x1c>;
395 reg = <0x1d>;
399 reg = <0x1e>;
403 reg = <0x1f>;
410 #size-cells = <0>;
413 gpios = <&gpio0 3 0>, <&gpio0 2 0>;
417 #size-cells = <0>;
420 phy11: ethernet-phy@0 {
422 reg = <0x0>;
428 #size-cells = <0>;
433 reg = <0x4>;