Lines Matching +full:0 +full:x4105
16 soc@0 {
26 * 1) Controller register (0 or 7)
27 * 2) Bit within the register (0..63)
29 #address-cells = <0>;
31 reg = <0x10701 0x00000000 0x0 0x4000000>;
37 reg = <0x10700 0x00000800 0x0 0x100>;
40 * 1) GPIO pin number (0..15)
49 interrupts = <7 0>, <7 1>, <7 2>, <7 3>,
58 #size-cells = <0>;
59 reg = <0x11800 0x00003800 0x0 0x40>;
65 <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
67 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
69 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
77 marvell,reg-init = <3 0x10 0 0x5777>,
78 <3 0x11 0 0x00aa>,
79 <3 0x12 0 0x4105>,
80 <3 0x13 0 0x0a60>;
86 marvell,reg-init = <3 0x10 0 0x5777>,
87 <3 0x11 0 0x00aa>,
88 <3 0x12 0 0x4105>,
89 <3 0x13 0 0x0a60>;
95 marvell,reg-init = <3 0x10 0 0x5777>,
96 <3 0x11 0 0x00aa>,
97 <3 0x12 0 0x4105>,
98 <3 0x13 0 0x0a60>;
104 marvell,reg-init = <3 0x10 0 0x5777>,
105 <3 0x11 0 0x00aa>,
106 <3 0x12 0 0x4105>,
107 <3 0x13 0 0x0a60>;
114 #size-cells = <0>;
115 reg = <0x11800 0x00003880 0x0 0x40>;
118 cavium,qlm-trim = "0,sgmii";
121 marvell,reg-init = <3 0x10 0 0x5777>,
122 <3 0x11 0 0x00aa>,
123 <3 0x12 0 0x4105>,
124 <3 0x13 0 0x0a60>;
127 cavium,qlm-trim = "0,sgmii";
130 marvell,reg-init = <3 0x10 0 0x5777>,
131 <3 0x11 0 0x00aa>,
132 <3 0x12 0 0x4105>,
133 <3 0x13 0 0x0a60>;
136 cavium,qlm-trim = "0,sgmii";
139 marvell,reg-init = <3 0x10 0 0x5777>,
140 <3 0x11 0 0x00aa>,
141 <3 0x12 0 0x4105>,
142 <3 0x13 0 0x0a60>;
145 cavium,qlm-trim = "0,sgmii";
148 marvell,reg-init = <3 0x10 0 0x5777>,
149 <3 0x11 0 0x00aa>,
150 <3 0x12 0 0x4105>,
151 <3 0x13 0 0x0a60>;
158 #size-cells = <0>;
159 reg = <0x11800 0x00003900 0x0 0x40>;
165 marvell,reg-init = <3 0x10 0 0x5777>,
166 <3 0x11 0 0x00aa>,
167 <3 0x12 0 0x4105>,
168 <3 0x13 0 0x0a60>;
174 marvell,reg-init = <3 0x10 0 0x5777>,
175 <3 0x11 0 0x00aa>,
176 <3 0x12 0 0x4105>,
177 <3 0x13 0 0x0a60>;
183 marvell,reg-init = <3 0x10 0 0x5777>,
184 <3 0x11 0 0x00aa>,
185 <3 0x12 0 0x4105>,
186 <3 0x13 0 0x0a60>;
192 marvell,reg-init = <3 0x10 0 0x5777>,
193 <3 0x11 0 0x00aa>,
194 <3 0x12 0 0x4105>,
195 <3 0x13 0 0x0a60>;
202 #size-cells = <0>;
203 reg = <0x11800 0x00003980 0x0 0x40>;
209 marvell,reg-init = <3 0x10 0 0x5777>,
210 <3 0x11 0 0x00aa>,
211 <3 0x12 0 0x4105>,
212 <3 0x13 0 0x0a60>;
218 marvell,reg-init = <3 0x10 0 0x5777>,
219 <3 0x11 0 0x00aa>,
220 <3 0x12 0 0x4105>,
221 <3 0x13 0 0x0a60>;
227 marvell,reg-init = <3 0x10 0 0x5777>,
228 <3 0x11 0 0x00aa>,
229 <3 0x12 0 0x4105>,
230 <3 0x13 0 0x0a60>;
236 marvell,reg-init = <3 0x10 0 0x5777>,
237 <3 0x11 0 0x00aa>,
238 <3 0x12 0 0x4105>,
239 <3 0x13 0 0x0a60>;
245 reg = <0x10700 0x00100000 0x0 0x100>, /* MIX */
246 <0x11800 0xE0000000 0x0 0x300>, /* AGL */
247 <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */
248 <0x11800 0xE0002000 0x0 0x8>; /* AGL_PRT_CTL */
249 cell-index = <0>;
258 #size-cells = <0>;
259 reg = <0x11800 0xa0000000 0x0 0x2000>;
264 #size-cells = <0>;
265 reg = <0x4>; /* interface */
267 ethernet@0 {
269 reg = <0x0>; /* Port */
275 reg = <0x1>; /* Port */
281 reg = <0x2>; /* Port */
287 reg = <0x3>; /* Port */
296 #size-cells = <0>;
297 reg = <0x3>; /* interface */
299 ethernet@0 {
301 reg = <0x0>; /* Port */
307 reg = <0x1>; /* Port */
313 reg = <0x2>; /* Port */
319 reg = <0x3>; /* Port */
328 #size-cells = <0>;
329 reg = <0x2>; /* interface */
331 ethernet@0 {
333 reg = <0x0>; /* Port */
339 reg = <0x1>; /* Port */
345 reg = <0x2>; /* Port */
351 reg = <0x3>; /* Port */
360 #size-cells = <0>;
361 reg = <0x1>; /* interface */
363 ethernet@0 {
365 reg = <0x0>; /* Port */
370 interface@0 {
373 #size-cells = <0>;
374 reg = <0x0>; /* interface */
376 ethernet@0 {
378 reg = <0x0>; /* Port */
384 reg = <0x1>; /* Port */
390 reg = <0x2>; /* Port */
396 reg = <0x3>; /* Port */
405 #size-cells = <0>;
407 reg = <0x11800 0x00001000 0x0 0x200>;
413 reg = <0x68>;
417 reg = <0x4c>;
423 #size-cells = <0>;
425 reg = <0x11800 0x00001200 0x0 0x200>;
432 reg = <0x11800 0x00000800 0x0 0x400>;
433 clock-frequency = <0>;
441 reg = <0x11800 0x00000c00 0x0 0x400>;
442 clock-frequency = <0>;
450 reg = <0x11800 0x00000000 0x0 0x200>;
455 ranges = <0 0 0 0x1f400000 0xc00000>,
456 <1 0 0x10000 0x30000000 0>,
457 <2 0 0x10000 0x40000000 0>,
458 <3 0 0x10000 0x50000000 0>,
459 <4 0 0 0x1d020000 0x10000>,
460 <5 0 0 0x1d040000 0x10000>,
461 <6 0 0 0x1d050000 0x10000>,
462 <7 0 0x10000 0x90000000 0>;
464 cavium,cs-config@0 {
466 cavium,cs-index = <0>;
473 cavium,t-pause = <0>;
476 cavium,t-rd-dly = <0>;
478 cavium,pages = <0>;
493 cavium,t-rd-dly = <0>;
495 cavium,pages = <0>;
501 cavium,t-adr = <0>;
507 cavium,t-pause = <0>;
510 cavium,t-rd-dly = <0>;
512 cavium,pages = <0>;
518 cavium,t-adr = <0>;
524 cavium,t-pause = <0>;
527 cavium,t-rd-dly = <0>;
529 cavium,pages = <0>;
534 flash0: nor@0,0 {
536 reg = <0 0 0x800000>;
540 partition@0 {
542 reg = <0 0x200000>;
547 reg = <0x200000 0x200000>;
551 reg = <0x400000 0x3fe000>;
555 reg = <0x7fe000 0x2000>;
560 led0: led-display@4,0 {
562 reg = <4 0x20 0x20>, <4 0 0x20>;
565 compact-flash@5,0 {
567 reg = <5 0 0x10000>, <6 0 0x10000>;
576 reg = <0x11800 0x00000100 0x0 0x8>;
577 interrupts = <0 63>;
581 reg = <0x11800 0x00000108 0x0 0x8>;
582 interrupts = <0 63>;
587 reg = <0x11800 0x6f000000 0x0 0x100>;
598 reg = <0x16f00 0x00000000 0x0 0x100>;
604 reg = <0x16f00 0x00000400 0x0 0x100>;