Lines Matching +full:mali +full:- +full:400
1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2014 - 2021, Xilinx, Inc.
15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
19 #include <dt-bindings/power/xlnx-zynqmp-power.h>
20 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
24 #address-cells = <2>;
25 #size-cells = <2>;
28 #address-cells = <1>;
29 #size-cells = <0>;
32 compatible = "arm,cortex-a53";
34 enable-method = "psci";
35 operating-points-v2 = <&cpu_opp_table>;
37 cpu-idle-states = <&CPU_SLEEP_0>;
38 next-level-cache = <&L2>;
42 compatible = "arm,cortex-a53";
44 enable-method = "psci";
46 operating-points-v2 = <&cpu_opp_table>;
47 cpu-idle-states = <&CPU_SLEEP_0>;
48 next-level-cache = <&L2>;
52 compatible = "arm,cortex-a53";
54 enable-method = "psci";
56 operating-points-v2 = <&cpu_opp_table>;
57 cpu-idle-states = <&CPU_SLEEP_0>;
58 next-level-cache = <&L2>;
62 compatible = "arm,cortex-a53";
64 enable-method = "psci";
66 operating-points-v2 = <&cpu_opp_table>;
67 cpu-idle-states = <&CPU_SLEEP_0>;
68 next-level-cache = <&L2>;
71 L2: l2-cache {
73 cache-level = <2>;
74 cache-unified;
77 idle-states {
78 entry-method = "psci";
80 CPU_SLEEP_0: cpu-sleep-0 {
81 compatible = "arm,idle-state";
82 arm,psci-suspend-param = <0x40000000>;
83 local-timer-stop;
84 entry-latency-us = <300>;
85 exit-latency-us = <600>;
86 min-residency-us = <10000>;
91 cpu_opp_table: opp-table-cpu {
92 compatible = "operating-points-v2";
93 opp-shared;
95 opp-hz = /bits/ 64 <1199999988>;
96 opp-microvolt = <1000000>;
97 clock-latency-ns = <500000>;
100 opp-hz = /bits/ 64 <599999994>;
101 opp-microvolt = <1000000>;
102 clock-latency-ns = <500000>;
105 opp-hz = /bits/ 64 <399999996>;
106 opp-microvolt = <1000000>;
107 clock-latency-ns = <500000>;
110 opp-hz = /bits/ 64 <299999997>;
111 opp-microvolt = <1000000>;
112 clock-latency-ns = <500000>;
116 reserved-memory {
117 #address-cells = <2>;
118 #size-cells = <2>;
122 no-map;
127 no-map;
132 zynqmp_ipi: zynqmp-ipi {
133 bootph-all;
134 compatible = "xlnx,zynqmp-ipi-mailbox";
135 interrupt-parent = <&gic>;
137 xlnx,ipi-id = <0>;
138 #address-cells = <2>;
139 #size-cells = <2>;
143 bootph-all;
144 compatible = "xlnx,zynqmp-ipi-dest-mailbox";
149 reg-names = "local_request_region",
153 #mbox-cells = <1>;
154 xlnx,ipi-id = <4>;
161 bootph-all;
165 compatible = "arm,armv8-pmuv3";
166 interrupt-parent = <&gic>;
171 interrupt-affinity = <&cpu0>,
178 compatible = "arm,psci-0.2";
183 zynqmp_firmware: zynqmp-firmware {
184 compatible = "xlnx,zynqmp-firmware";
185 #power-domain-cells = <1>;
187 bootph-all;
189 zynqmp_power: zynqmp-power {
190 bootph-all;
191 compatible = "xlnx,zynqmp-power";
192 interrupt-parent = <&gic>;
195 mbox-names = "tx", "rx";
198 nvmem-firmware {
199 compatible = "xlnx,zynqmp-nvmem-fw";
200 #address-cells = <1>;
201 #size-cells = <1>;
203 soc_revision: soc-revision@0 {
209 compatible = "xlnx,zynqmp-pcap-fpga";
212 xlnx_aes: zynqmp-aes {
213 compatible = "xlnx,zynqmp-aes";
216 zynqmp_reset: reset-controller {
217 compatible = "xlnx,zynqmp-reset";
218 #reset-cells = <1>;
222 compatible = "xlnx,zynqmp-pinctrl";
227 compatible = "xlnx,zynqmp-gpio-modepin";
228 gpio-controller;
229 #gpio-cells = <2>;
235 compatible = "arm,armv8-timer";
236 interrupt-parent = <&gic>;
243 fpga_full: fpga-full {
244 compatible = "fpga-region";
245 fpga-mgr = <&zynqmp_pcap>;
246 #address-cells = <2>;
247 #size-cells = <2>;
252 compatible = "xlnx,zynqmp-r5fss";
253 xlnx,cluster-mode = <1>;
255 r5f-0 {
256 compatible = "xlnx,zynqmp-r5f";
257 power-domains = <&zynqmp_firmware PD_RPU_0>;
258 memory-region = <&rproc_0_fw_image>;
261 r5f-1 {
262 compatible = "xlnx,zynqmp-r5f";
263 power-domains = <&zynqmp_firmware PD_RPU_1>;
264 memory-region = <&rproc_1_fw_image>;
269 compatible = "simple-bus";
270 bootph-all;
271 #address-cells = <2>;
272 #size-cells = <2>;
276 compatible = "xlnx,zynq-can-1.0";
278 clock-names = "can_clk", "pclk";
281 interrupt-parent = <&gic>;
282 tx-fifo-depth = <0x40>;
283 rx-fifo-depth = <0x40>;
284 power-domains = <&zynqmp_firmware PD_CAN_0>;
288 compatible = "xlnx,zynq-can-1.0";
290 clock-names = "can_clk", "pclk";
293 interrupt-parent = <&gic>;
294 tx-fifo-depth = <0x40>;
295 rx-fifo-depth = <0x40>;
296 power-domains = <&zynqmp_firmware PD_CAN_1>;
300 compatible = "arm,cci-400";
304 #address-cells = <1>;
305 #size-cells = <1>;
308 compatible = "arm,cci-400-pmu,r1";
310 interrupt-parent = <&gic>;
320 fpd_dma_chan1: dma-controller@fd500000 {
322 compatible = "xlnx,zynqmp-dma-1.0";
324 interrupt-parent = <&gic>;
326 clock-names = "clk_main", "clk_apb";
327 #dma-cells = <1>;
328 xlnx,bus-width = <128>;
330 power-domains = <&zynqmp_firmware PD_GDMA>;
333 fpd_dma_chan2: dma-controller@fd510000 {
335 compatible = "xlnx,zynqmp-dma-1.0";
337 interrupt-parent = <&gic>;
339 clock-names = "clk_main", "clk_apb";
340 #dma-cells = <1>;
341 xlnx,bus-width = <128>;
343 power-domains = <&zynqmp_firmware PD_GDMA>;
346 fpd_dma_chan3: dma-controller@fd520000 {
348 compatible = "xlnx,zynqmp-dma-1.0";
350 interrupt-parent = <&gic>;
352 clock-names = "clk_main", "clk_apb";
353 #dma-cells = <1>;
354 xlnx,bus-width = <128>;
356 power-domains = <&zynqmp_firmware PD_GDMA>;
359 fpd_dma_chan4: dma-controller@fd530000 {
361 compatible = "xlnx,zynqmp-dma-1.0";
363 interrupt-parent = <&gic>;
365 clock-names = "clk_main", "clk_apb";
366 #dma-cells = <1>;
367 xlnx,bus-width = <128>;
369 power-domains = <&zynqmp_firmware PD_GDMA>;
372 fpd_dma_chan5: dma-controller@fd540000 {
374 compatible = "xlnx,zynqmp-dma-1.0";
376 interrupt-parent = <&gic>;
378 clock-names = "clk_main", "clk_apb";
379 #dma-cells = <1>;
380 xlnx,bus-width = <128>;
382 power-domains = <&zynqmp_firmware PD_GDMA>;
385 fpd_dma_chan6: dma-controller@fd550000 {
387 compatible = "xlnx,zynqmp-dma-1.0";
389 interrupt-parent = <&gic>;
391 clock-names = "clk_main", "clk_apb";
392 #dma-cells = <1>;
393 xlnx,bus-width = <128>;
395 power-domains = <&zynqmp_firmware PD_GDMA>;
398 fpd_dma_chan7: dma-controller@fd560000 {
400 compatible = "xlnx,zynqmp-dma-1.0";
402 interrupt-parent = <&gic>;
404 clock-names = "clk_main", "clk_apb";
405 #dma-cells = <1>;
406 xlnx,bus-width = <128>;
408 power-domains = <&zynqmp_firmware PD_GDMA>;
411 fpd_dma_chan8: dma-controller@fd570000 {
413 compatible = "xlnx,zynqmp-dma-1.0";
415 interrupt-parent = <&gic>;
417 clock-names = "clk_main", "clk_apb";
418 #dma-cells = <1>;
419 xlnx,bus-width = <128>;
421 power-domains = <&zynqmp_firmware PD_GDMA>;
424 gic: interrupt-controller@f9010000 {
425 compatible = "arm,gic-400";
426 #interrupt-cells = <3>;
431 interrupt-controller;
432 interrupt-parent = <&gic>;
438 compatible = "xlnx,zynqmp-mali", "arm,mali-400";
440 interrupt-parent = <&gic>;
447 interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", "ppmmu1";
448 clock-names = "bus", "core";
449 power-domains = <&zynqmp_firmware PD_GPU>;
456 lpd_dma_chan1: dma-controller@ffa80000 {
458 compatible = "xlnx,zynqmp-dma-1.0";
460 interrupt-parent = <&gic>;
462 clock-names = "clk_main", "clk_apb";
463 #dma-cells = <1>;
464 xlnx,bus-width = <64>;
466 power-domains = <&zynqmp_firmware PD_ADMA>;
469 lpd_dma_chan2: dma-controller@ffa90000 {
471 compatible = "xlnx,zynqmp-dma-1.0";
473 interrupt-parent = <&gic>;
475 clock-names = "clk_main", "clk_apb";
476 #dma-cells = <1>;
477 xlnx,bus-width = <64>;
479 power-domains = <&zynqmp_firmware PD_ADMA>;
482 lpd_dma_chan3: dma-controller@ffaa0000 {
484 compatible = "xlnx,zynqmp-dma-1.0";
486 interrupt-parent = <&gic>;
488 clock-names = "clk_main", "clk_apb";
489 #dma-cells = <1>;
490 xlnx,bus-width = <64>;
492 power-domains = <&zynqmp_firmware PD_ADMA>;
495 lpd_dma_chan4: dma-controller@ffab0000 {
497 compatible = "xlnx,zynqmp-dma-1.0";
499 interrupt-parent = <&gic>;
501 clock-names = "clk_main", "clk_apb";
502 #dma-cells = <1>;
503 xlnx,bus-width = <64>;
505 power-domains = <&zynqmp_firmware PD_ADMA>;
508 lpd_dma_chan5: dma-controller@ffac0000 {
510 compatible = "xlnx,zynqmp-dma-1.0";
512 interrupt-parent = <&gic>;
514 clock-names = "clk_main", "clk_apb";
515 #dma-cells = <1>;
516 xlnx,bus-width = <64>;
518 power-domains = <&zynqmp_firmware PD_ADMA>;
521 lpd_dma_chan6: dma-controller@ffad0000 {
523 compatible = "xlnx,zynqmp-dma-1.0";
525 interrupt-parent = <&gic>;
527 clock-names = "clk_main", "clk_apb";
528 #dma-cells = <1>;
529 xlnx,bus-width = <64>;
531 power-domains = <&zynqmp_firmware PD_ADMA>;
534 lpd_dma_chan7: dma-controller@ffae0000 {
536 compatible = "xlnx,zynqmp-dma-1.0";
538 interrupt-parent = <&gic>;
540 clock-names = "clk_main", "clk_apb";
541 #dma-cells = <1>;
542 xlnx,bus-width = <64>;
544 power-domains = <&zynqmp_firmware PD_ADMA>;
547 lpd_dma_chan8: dma-controller@ffaf0000 {
549 compatible = "xlnx,zynqmp-dma-1.0";
551 interrupt-parent = <&gic>;
553 clock-names = "clk_main", "clk_apb";
554 #dma-cells = <1>;
555 xlnx,bus-width = <64>;
557 power-domains = <&zynqmp_firmware PD_ADMA>;
560 mc: memory-controller@fd070000 {
561 compatible = "xlnx,zynqmp-ddrc-2.40a";
563 interrupt-parent = <&gic>;
567 nand0: nand-controller@ff100000 {
568 compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10";
571 clock-names = "controller", "bus";
572 interrupt-parent = <&gic>;
574 #address-cells = <1>;
575 #size-cells = <0>;
577 power-domains = <&zynqmp_firmware PD_NAND>;
581 compatible = "xlnx,zynqmp-gem", "cdns,gem";
583 interrupt-parent = <&gic>;
587 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
589 power-domains = <&zynqmp_firmware PD_ETH_0>;
591 reset-names = "gem0_rst";
595 compatible = "xlnx,zynqmp-gem", "cdns,gem";
597 interrupt-parent = <&gic>;
601 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
603 power-domains = <&zynqmp_firmware PD_ETH_1>;
605 reset-names = "gem1_rst";
609 compatible = "xlnx,zynqmp-gem", "cdns,gem";
611 interrupt-parent = <&gic>;
615 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
617 power-domains = <&zynqmp_firmware PD_ETH_2>;
619 reset-names = "gem2_rst";
623 compatible = "xlnx,zynqmp-gem", "cdns,gem";
625 interrupt-parent = <&gic>;
629 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
631 power-domains = <&zynqmp_firmware PD_ETH_3>;
633 reset-names = "gem3_rst";
637 compatible = "xlnx,zynqmp-gpio-1.0";
639 #gpio-cells = <0x2>;
640 gpio-controller;
641 interrupt-parent = <&gic>;
643 interrupt-controller;
644 #interrupt-cells = <2>;
646 power-domains = <&zynqmp_firmware PD_GPIO>;
650 compatible = "cdns,i2c-r1p14";
652 interrupt-parent = <&gic>;
654 clock-frequency = <400000>;
656 #address-cells = <1>;
657 #size-cells = <0>;
658 power-domains = <&zynqmp_firmware PD_I2C_0>;
662 compatible = "cdns,i2c-r1p14";
664 interrupt-parent = <&gic>;
666 clock-frequency = <400000>;
668 #address-cells = <1>;
669 #size-cells = <0>;
670 power-domains = <&zynqmp_firmware PD_I2C_1>;
674 compatible = "xlnx,nwl-pcie-2.11";
676 #address-cells = <3>;
677 #size-cells = <2>;
678 #interrupt-cells = <1>;
679 msi-controller;
681 interrupt-parent = <&gic>;
687 interrupt-names = "misc", "dummy", "intx",
689 msi-parent = <&pcie>;
693 reg-names = "breg", "pcireg", "cfg";
694 ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-prefetchable memory */
696 bus-range = <0x00 0xff>;
697 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
698 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
703 power-domains = <&zynqmp_firmware PD_PCIE>;
704 pcie_intc: legacy-interrupt-controller {
705 interrupt-controller;
706 #address-cells = <0>;
707 #interrupt-cells = <1>;
712 bootph-all;
713 compatible = "xlnx,zynqmp-qspi-1.0";
715 clock-names = "ref_clk", "pclk";
717 interrupt-parent = <&gic>;
718 num-cs = <1>;
721 #address-cells = <1>;
722 #size-cells = <0>;
724 power-domains = <&zynqmp_firmware PD_QSPI>;
728 compatible = "xlnx,zynqmp-psgtr-v1.1";
732 reg-names = "serdes", "siou";
733 #phy-cells = <4>;
737 compatible = "xlnx,zynqmp-rtc";
740 interrupt-parent = <&gic>;
743 interrupt-names = "alarm", "sec";
748 compatible = "ceva,ahci-1v84";
751 interrupt-parent = <&gic>;
753 power-domains = <&zynqmp_firmware PD_SATA>;
760 bootph-all;
761 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
763 interrupt-parent = <&gic>;
766 clock-names = "clk_xin", "clk_ahb";
768 #clock-cells = <1>;
769 clock-output-names = "clk_out_sd0", "clk_in_sd0";
770 power-domains = <&zynqmp_firmware PD_SD_0>;
775 bootph-all;
776 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
778 interrupt-parent = <&gic>;
781 clock-names = "clk_xin", "clk_ahb";
783 #clock-cells = <1>;
784 clock-output-names = "clk_out_sd1", "clk_in_sd1";
785 power-domains = <&zynqmp_firmware PD_SD_1>;
790 compatible = "arm,mmu-500";
792 #iommu-cells = <1>;
794 #global-interrupts = <1>;
795 interrupt-parent = <&gic>;
816 compatible = "cdns,spi-r1p6";
818 interrupt-parent = <&gic>;
821 clock-names = "ref_clk", "pclk";
822 #address-cells = <1>;
823 #size-cells = <0>;
824 power-domains = <&zynqmp_firmware PD_SPI_0>;
828 compatible = "cdns,spi-r1p6";
830 interrupt-parent = <&gic>;
833 clock-names = "ref_clk", "pclk";
834 #address-cells = <1>;
835 #size-cells = <0>;
836 power-domains = <&zynqmp_firmware PD_SPI_1>;
842 interrupt-parent = <&gic>;
847 timer-width = <32>;
848 power-domains = <&zynqmp_firmware PD_TTC_0>;
854 interrupt-parent = <&gic>;
859 timer-width = <32>;
860 power-domains = <&zynqmp_firmware PD_TTC_1>;
866 interrupt-parent = <&gic>;
871 timer-width = <32>;
872 power-domains = <&zynqmp_firmware PD_TTC_2>;
878 interrupt-parent = <&gic>;
883 timer-width = <32>;
884 power-domains = <&zynqmp_firmware PD_TTC_3>;
888 bootph-all;
889 compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
891 interrupt-parent = <&gic>;
894 clock-names = "uart_clk", "pclk";
895 power-domains = <&zynqmp_firmware PD_UART_0>;
899 bootph-all;
900 compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
902 interrupt-parent = <&gic>;
905 clock-names = "uart_clk", "pclk";
906 power-domains = <&zynqmp_firmware PD_UART_1>;
910 #address-cells = <2>;
911 #size-cells = <2>;
913 compatible = "xlnx,zynqmp-dwc3";
915 power-domains = <&zynqmp_firmware PD_USB_0>;
919 reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
920 reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>;
926 interrupt-parent = <&gic>;
927 interrupt-names = "host", "peripheral", "otg";
931 clock-names = "bus_early", "ref";
933 snps,quirk-frame-length-adjustment = <0x20>;
934 snps,resume-hs-terminations;
935 /* dma-coherent; */
940 #address-cells = <2>;
941 #size-cells = <2>;
943 compatible = "xlnx,zynqmp-dwc3";
945 power-domains = <&zynqmp_firmware PD_USB_1>;
949 reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
955 interrupt-parent = <&gic>;
956 interrupt-names = "host", "peripheral", "otg";
960 clock-names = "bus_early", "ref";
962 snps,quirk-frame-length-adjustment = <0x20>;
963 snps,resume-hs-terminations;
964 /* dma-coherent; */
969 compatible = "cdns,wdt-r1p2";
971 interrupt-parent = <&gic>;
974 timeout-sec = <60>;
975 reset-on-timeout;
979 compatible = "cdns,wdt-r1p2";
981 interrupt-parent = <&gic>;
984 timeout-sec = <10>;
988 compatible = "xlnx,zynqmp-ams";
990 interrupt-parent = <&gic>;
993 #address-cells = <1>;
994 #size-cells = <1>;
995 #io-channel-cells = <1>;
998 ams_ps: ams-ps@0 {
999 compatible = "xlnx,zynqmp-ams-ps";
1004 ams_pl: ams-pl@400 {
1005 compatible = "xlnx,zynqmp-ams-pl";
1008 #address-cells = <1>;
1009 #size-cells = <0>;
1013 zynqmp_dpdma: dma-controller@fd4c0000 {
1014 compatible = "xlnx,zynqmp-dpdma";
1018 interrupt-parent = <&gic>;
1019 clock-names = "axi_clk";
1020 power-domains = <&zynqmp_firmware PD_DP>;
1021 #dma-cells = <1>;
1025 bootph-all;
1026 compatible = "xlnx,zynqmp-dpsub-1.7";
1032 reg-names = "dp", "blend", "av_buf", "aud";
1034 interrupt-parent = <&gic>;
1035 clock-names = "dp_apb_clk", "dp_aud_clk",
1037 power-domains = <&zynqmp_firmware PD_DP>;
1039 dma-names = "vid0", "vid1", "vid2", "gfx0";
1046 #address-cells = <1>;
1047 #size-cells = <0>;