Lines Matching +full:tslch +full:- +full:ns
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
10 #include "k3-j721s2.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
22 reserved_memory: reserved-memory {
23 #address-cells = <2>;
24 #size-cells = <2>;
30 no-map;
33 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
34 compatible = "shared-dma-pool";
36 no-map;
39 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
40 compatible = "shared-dma-pool";
42 no-map;
45 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
46 compatible = "shared-dma-pool";
48 no-map;
51 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
52 compatible = "shared-dma-pool";
54 no-map;
57 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
58 compatible = "shared-dma-pool";
60 no-map;
63 main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
64 compatible = "shared-dma-pool";
66 no-map;
69 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
70 compatible = "shared-dma-pool";
72 no-map;
75 main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
76 compatible = "shared-dma-pool";
78 no-map;
81 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
82 compatible = "shared-dma-pool";
84 no-map;
87 main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
88 compatible = "shared-dma-pool";
90 no-map;
93 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
94 compatible = "shared-dma-pool";
96 no-map;
99 main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
100 compatible = "shared-dma-pool";
102 no-map;
105 c71_0_dma_memory_region: c71-dma-memory@a6000000 {
106 compatible = "shared-dma-pool";
108 no-map;
111 c71_0_memory_region: c71-memory@a6100000 {
112 compatible = "shared-dma-pool";
114 no-map;
117 c71_1_dma_memory_region: c71-dma-memory@a7000000 {
118 compatible = "shared-dma-pool";
120 no-map;
123 c71_1_memory_region: c71-memory@a7100000 {
124 compatible = "shared-dma-pool";
126 no-map;
129 rtos_ipc_memory_region: ipc-memories@a8000000 {
132 no-map;
136 mux0: mux-controller {
137 compatible = "gpio-mux";
138 #mux-state-cells = <1>;
139 mux-gpios = <&exp_som 1 GPIO_ACTIVE_HIGH>;
142 mux1: mux-controller {
143 compatible = "gpio-mux";
144 #mux-state-cells = <1>;
145 mux-gpios = <&exp_som 2 GPIO_ACTIVE_HIGH>;
148 transceiver0: can-phy0 {
151 #phy-cells = <0>;
152 max-bitrate = <5000000>;
157 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
158 pinctrl-single,pins = <
176 pmic_irq_pins_default: pmic-irq-default-pins {
177 pinctrl-single,pins = <
185 wkup_i2c0_pins_default: wkup-i2c0-default-pins {
186 pinctrl-single,pins = <
194 main_i2c0_pins_default: main-i2c0-default-pins {
195 pinctrl-single,pins = <
201 main_mcan16_pins_default: main-mcan16-default-pins {
202 pinctrl-single,pins = <
211 pinctrl-names = "default";
212 pinctrl-0 = <&wkup_i2c0_pins_default>;
213 clock-frequency = <400000>;
216 /* CAV24C256WE-GT3 */
222 compatible = "ti,tps6594-q1";
224 system-power-controller;
225 pinctrl-names = "default";
226 pinctrl-0 = <&pmic_irq_pins_default>;
227 interrupt-parent = <&wkup_gpio0>;
229 gpio-controller;
230 #gpio-cells = <2>;
231 ti,primary-pmic;
232 buck1234-supply = <&vsys_3v3>;
233 buck5-supply = <&vsys_3v3>;
234 ldo1-supply = <&vsys_3v3>;
235 ldo2-supply = <&vsys_3v3>;
236 ldo3-supply = <&vsys_3v3>;
237 ldo4-supply = <&vsys_3v3>;
241 regulator-name = "vdd_cpu_avs";
242 regulator-min-microvolt = <600000>;
243 regulator-max-microvolt = <900000>;
244 regulator-boot-on;
245 regulator-always-on;
246 bootph-pre-ram;
250 regulator-name = "vdd_mcu_0v85";
251 regulator-min-microvolt = <850000>;
252 regulator-max-microvolt = <850000>;
253 regulator-boot-on;
254 regulator-always-on;
258 regulator-name = "vdd_mcuwk_0v8";
259 regulator-min-microvolt = <800000>;
260 regulator-max-microvolt = <800000>;
261 regulator-boot-on;
262 regulator-always-on;
266 regulator-name = "vdd_mcu_gpioret_3v3";
267 regulator-min-microvolt = <3300000>;
268 regulator-max-microvolt = <3300000>;
269 regulator-boot-on;
270 regulator-always-on;
274 regulator-name = "vdd_mcuio_1v8";
275 regulator-min-microvolt = <1800000>;
276 regulator-max-microvolt = <1800000>;
277 regulator-boot-on;
278 regulator-always-on;
282 regulator-name = "vda_mcu_1v8";
283 regulator-min-microvolt = <1800000>;
284 regulator-max-microvolt = <1800000>;
285 regulator-boot-on;
286 regulator-always-on;
292 compatible = "ti,tps6594-q1";
294 system-power-controller;
295 interrupt-parent = <&wkup_gpio0>;
297 gpio-controller;
298 #gpio-cells = <2>;
299 buck1-supply = <&vsys_3v3>;
300 buck2-supply = <&vsys_3v3>;
301 buck3-supply = <&vsys_3v3>;
302 buck4-supply = <&vsys_3v3>;
303 buck5-supply = <&vsys_3v3>;
304 ldo1-supply = <&vsys_3v3>;
305 ldo2-supply = <&vsys_3v3>;
306 ldo3-supply = <&vsys_3v3>;
307 ldo4-supply = <&vsys_3v3>;
311 regulator-name = "vdd_io_1v8_reg";
312 regulator-min-microvolt = <1800000>;
313 regulator-max-microvolt = <1800000>;
314 regulator-always-on;
315 regulator-boot-on;
319 regulator-name = "vdd_fpd_1v1";
320 regulator-min-microvolt = <1100000>;
321 regulator-max-microvolt = <1100000>;
322 regulator-boot-on;
323 regulator-always-on;
327 regulator-name = "vdd_phy_1v8";
328 regulator-min-microvolt = <1800000>;
329 regulator-max-microvolt = <1800000>;
330 regulator-boot-on;
331 regulator-always-on;
335 regulator-name = "vdd_ddr_1v1";
336 regulator-min-microvolt = <1100000>;
337 regulator-max-microvolt = <1100000>;
338 regulator-boot-on;
339 regulator-always-on;
343 regulator-name = "vdd_ram_0v85";
344 regulator-min-microvolt = <850000>;
345 regulator-max-microvolt = <850000>;
346 regulator-boot-on;
347 regulator-always-on;
351 regulator-name = "vdd_wk_0v8";
352 regulator-min-microvolt = <800000>;
353 regulator-max-microvolt = <800000>;
354 regulator-boot-on;
355 regulator-always-on;
359 regulator-name = "vdd_gpioret_3v3";
360 regulator-min-microvolt = <3300000>;
361 regulator-max-microvolt = <3300000>;
362 regulator-boot-on;
363 regulator-always-on;
367 regulator-name = "vda_dll_0v8";
368 regulator-min-microvolt = <800000>;
369 regulator-max-microvolt = <800000>;
370 regulator-boot-on;
371 regulator-always-on;
375 regulator-name = "vda_pll_1v8";
376 regulator-min-microvolt = <1800000>;
377 regulator-max-microvolt = <1800000>;
378 regulator-boot-on;
379 regulator-always-on;
385 compatible = "ti,lp8764-q1";
387 system-power-controller;
388 interrupt-parent = <&wkup_gpio0>;
390 gpio-controller;
391 #gpio-cells = <2>;
392 buck1234-supply = <&vsys_3v3>;
396 regulator-name = "vdd_core_0v8";
397 regulator-min-microvolt = <800000>;
398 regulator-max-microvolt = <800000>;
399 regulator-boot-on;
400 regulator-always-on;
408 pinctrl-names = "default";
409 pinctrl-0 = <&main_i2c0_pins_default>;
410 clock-frequency = <400000>;
415 gpio-controller;
416 #gpio-cells = <2>;
417 gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0",
426 pinctrl-0 = <&main_mcan16_pins_default>;
427 pinctrl-names = "default";
433 pinctrl-names = "default";
434 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
437 compatible = "jedec,spi-nor";
439 spi-tx-bus-width = <8>;
440 spi-rx-bus-width = <8>;
441 spi-max-frequency = <25000000>;
442 cdns,tshsl-ns = <60>;
443 cdns,tsd2d-ns = <60>;
444 cdns,tchsh-ns = <60>;
445 cdns,tslch-ns = <60>;
446 cdns,read-delay = <4>;
453 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
454 ti,mbox-rx = <0 0 0>;
455 ti,mbox-tx = <1 0 0>;
458 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
459 ti,mbox-rx = <2 0 0>;
460 ti,mbox-tx = <3 0 0>;
467 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
468 ti,mbox-rx = <0 0 0>;
469 ti,mbox-tx = <1 0 0>;
472 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
473 ti,mbox-rx = <2 0 0>;
474 ti,mbox-tx = <3 0 0>;
481 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
482 ti,mbox-rx = <0 0 0>;
483 ti,mbox-tx = <1 0 0>;
486 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
487 ti,mbox-rx = <2 0 0>;
488 ti,mbox-tx = <3 0 0>;
495 mbox_c71_0: mbox-c71-0 {
496 ti,mbox-rx = <0 0 0>;
497 ti,mbox-tx = <1 0 0>;
500 mbox_c71_1: mbox-c71-1 {
501 ti,mbox-rx = <2 0 0>;
502 ti,mbox-tx = <3 0 0>;
508 memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
514 memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
520 memory-region = <&main_r5fss0_core0_dma_memory_region>,
526 memory-region = <&main_r5fss0_core1_dma_memory_region>,
532 memory-region = <&main_r5fss1_core0_dma_memory_region>,
538 memory-region = <&main_r5fss1_core1_dma_memory_region>,
545 memory-region = <&c71_0_dma_memory_region>,
552 memory-region = <&c71_1_dma_memory_region>,