Lines Matching +full:k2g +full:- +full:sci
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
9 dmsc: system-controller@44083000 {
10 compatible = "ti,k2g-sci";
11 ti,host-id = <12>;
13 mbox-names = "rx", "tx";
18 reg-names = "debug_messages";
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
23 #power-domain-cells = <2>;
26 k3_clks: clock-controller {
27 compatible = "ti,k2g-sci-clk";
28 #clock-cells = <2>;
31 k3_reset: reset-controller {
32 compatible = "ti,sci-reset";
33 #reset-cells = <2>;
39 compatible = "ti,am654-timer";
43 clock-names = "fck";
44 assigned-clocks = <&k3_clks 35 1>;
45 assigned-clock-parents = <&k3_clks 35 2>;
46 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
47 ti,timer-pwm;
52 compatible = "ti,am654-timer";
56 clock-names = "fck";
57 assigned-clocks = <&k3_clks 71 1>, <&k3_clks 308 0>;
58 assigned-clock-parents = <&k3_clks 71 2>, <&k3_clks 308 1>;
59 power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>;
60 ti,timer-pwm;
65 compatible = "ti,am654-timer";
69 clock-names = "fck";
70 assigned-clocks = <&k3_clks 72 1>;
71 assigned-clock-parents = <&k3_clks 72 2>;
72 power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>;
73 ti,timer-pwm;
78 compatible = "ti,am654-timer";
82 clock-names = "fck";
83 assigned-clocks = <&k3_clks 73 1>, <&k3_clks 309 0>;
84 assigned-clock-parents = <&k3_clks 73 2>, <&k3_clks 309 1>;
85 power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>;
86 ti,timer-pwm;
91 compatible = "ti,am654-timer";
95 clock-names = "fck";
96 assigned-clocks = <&k3_clks 74 1>;
97 assigned-clock-parents = <&k3_clks 74 2>;
98 power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>;
99 ti,timer-pwm;
104 compatible = "ti,am654-timer";
108 clock-names = "fck";
109 assigned-clocks = <&k3_clks 75 1>, <&k3_clks 310 0>;
110 assigned-clock-parents = <&k3_clks 75 2>, <&k3_clks 310 1>;
111 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
112 ti,timer-pwm;
117 compatible = "ti,am654-timer";
121 clock-names = "fck";
122 assigned-clocks = <&k3_clks 76 1>;
123 assigned-clock-parents = <&k3_clks 76 2>;
124 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
125 ti,timer-pwm;
130 compatible = "ti,am654-timer";
134 clock-names = "fck";
135 assigned-clocks = <&k3_clks 77 1>, <&k3_clks 311 0>;
136 assigned-clock-parents = <&k3_clks 77 2>, <&k3_clks 311 1>;
137 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
138 ti,timer-pwm;
143 compatible = "ti,am654-timer";
147 clock-names = "fck";
148 assigned-clocks = <&k3_clks 78 1>;
149 assigned-clock-parents = <&k3_clks 78 2>;
150 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
151 ti,timer-pwm;
156 compatible = "ti,am654-timer";
160 clock-names = "fck";
161 assigned-clocks = <&k3_clks 79 1>, <&k3_clks 312 0>;
162 assigned-clock-parents = <&k3_clks 79 2>, <&k3_clks 312 1>;
163 power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
164 ti,timer-pwm;
168 compatible = "syscon", "simple-mfd";
170 #address-cells = <1>;
171 #size-cells = <1>;
175 compatible = "ti,am654-phy-gmii-sel";
177 #phy-cells = <1>;
182 compatible = "simple-bus";
183 #address-cells = <1>;
184 #size-cells = <1>;
188 compatible = "ti,am654-chipid";
195 compatible = "pinctrl-single";
197 #pinctrl-cells = <1>;
198 pinctrl-single,register-width = <32>;
199 pinctrl-single,function-mask = <0x0000000F>;
205 compatible = "pinctrl-single";
207 #pinctrl-cells = <1>;
208 pinctrl-single,register-width = <32>;
209 pinctrl-single,function-mask = <0x0000000F>;
214 compatible = "pinctrl-single";
217 #pinctrl-cells = <1>;
218 pinctrl-single,register-width = <32>;
219 pinctrl-single,function-mask = <0xffffffff>;
223 compatible = "pinctrl-single";
226 #pinctrl-cells = <1>;
227 pinctrl-single,register-width = <32>;
228 pinctrl-single,function-mask = <0xffffffff>;
232 compatible = "pinctrl-single";
235 #pinctrl-cells = <1>;
236 pinctrl-single,register-width = <32>;
237 pinctrl-single,function-mask = <0xffffffff>;
241 compatible = "pinctrl-single";
244 #pinctrl-cells = <1>;
245 pinctrl-single,register-width = <32>;
246 pinctrl-single,function-mask = <0xffffffff>;
250 compatible = "mmio-sram";
253 #address-cells = <1>;
254 #size-cells = <1>;
258 compatible = "ti,j721e-uart", "ti,am654-uart";
261 clock-frequency = <48000000>;
262 current-speed = <115200>;
263 power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
265 clock-names = "fclk";
270 compatible = "ti,j721e-uart", "ti,am654-uart";
273 clock-frequency = <96000000>;
274 current-speed = <115200>;
275 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
277 clock-names = "fclk";
281 wkup_gpio_intr: interrupt-controller@42200000 {
282 compatible = "ti,sci-intr";
284 ti,intr-trigger-type = <1>;
285 interrupt-controller;
286 interrupt-parent = <&gic500>;
287 #interrupt-cells = <1>;
288 ti,sci = <&dmsc>;
289 ti,sci-dev-id = <137>;
290 ti,interrupt-ranges = <16 960 16>;
294 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
296 gpio-controller;
297 #gpio-cells = <2>;
298 interrupt-parent = <&wkup_gpio_intr>;
300 interrupt-controller;
301 #interrupt-cells = <2>;
303 ti,davinci-gpio-unbanked = <0>;
304 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
306 clock-names = "gpio";
311 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
313 gpio-controller;
314 #gpio-cells = <2>;
315 interrupt-parent = <&wkup_gpio_intr>;
317 interrupt-controller;
318 #interrupt-cells = <2>;
320 ti,davinci-gpio-unbanked = <0>;
321 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
323 clock-names = "gpio";
328 compatible = "simple-bus";
329 #address-cells = <2>;
330 #size-cells = <2>;
332 dma-coherent;
333 dma-ranges;
334 ti,sci-dev-id = <232>;
337 compatible = "ti,am654-navss-ringacc";
343 reg-names = "rt", "fifos", "proxy_gcfg",
345 ti,num-rings = <286>;
346 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
347 ti,sci = <&dmsc>;
348 ti,sci-dev-id = <235>;
349 msi-parent = <&main_udmass_inta>;
352 mcu_udmap: dma-controller@285c0000 {
353 compatible = "ti,j721e-navss-mcu-udmap";
360 reg-names = "gcfg", "rchanrt", "tchanrt",
362 msi-parent = <&main_udmass_inta>;
363 #dma-cells = <1>;
365 ti,sci = <&dmsc>;
366 ti,sci-dev-id = <236>;
369 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
371 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
373 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
378 compatible = "ti,am654-secure-proxy";
379 #mbox-cells = <1>;
380 reg-names = "target_data", "rt", "scfg";
387 * firmware on non-MPU processors
393 compatible = "ti,j721e-cpsw-nuss";
394 #address-cells = <2>;
395 #size-cells = <2>;
397 reg-names = "cpsw_nuss";
399 dma-coherent;
401 clock-names = "fck";
402 power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;
413 dma-names = "tx0", "tx1", "tx2", "tx3",
417 ethernet-ports {
418 #address-cells = <1>;
419 #size-cells = <0>;
423 ti,mac-only;
425 ti,syscon-efuse = <&mcu_conf 0x200>;
431 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
433 #address-cells = <1>;
434 #size-cells = <0>;
436 clock-names = "fck";
441 compatible = "ti,am65-cpts";
444 clock-names = "cpts";
445 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
446 interrupt-names = "cpts";
447 ti,cpts-ext-ts-inputs = <4>;
448 ti,cpts-periodic-outputs = <2>;
453 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
456 #address-cells = <1>;
457 #size-cells = <0>;
458 clock-names = "fck";
460 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
465 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
468 #address-cells = <1>;
469 #size-cells = <0>;
470 clock-names = "fck";
472 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
477 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
480 #address-cells = <1>;
481 #size-cells = <0>;
482 clock-names = "fck";
484 power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>;
489 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
492 #address-cells = <1>;
493 #size-cells = <0>;
494 power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>;
500 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
503 #address-cells = <1>;
504 #size-cells = <0>;
505 power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>;
511 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
514 #address-cells = <1>;
515 #size-cells = <0>;
516 power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
522 compatible = "syscon", "simple-mfd";
524 #address-cells = <2>;
525 #size-cells = <2>;
528 hbmc_mux: hbmc-mux {
529 compatible = "mmio-mux";
530 #mux-control-cells = <1>;
531 mux-reg-masks = <0x4 0x2>; /* HBMC select */
535 compatible = "ti,am654-hbmc";
538 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
540 assigned-clocks = <&k3_clks 102 5>;
541 assigned-clock-rates = <333333333>;
542 #address-cells = <2>;
543 #size-cells = <1>;
544 mux-controls = <&hbmc_mux 0>;
548 compatible = "ti,am654-ospi", "cdns,qspi-nor";
552 cdns,fifo-depth = <256>;
553 cdns,fifo-width = <4>;
554 cdns,trigger-address = <0x0>;
556 assigned-clocks = <&k3_clks 103 0>;
557 assigned-clock-parents = <&k3_clks 103 2>;
558 assigned-clock-rates = <166666666>;
559 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
560 #address-cells = <1>;
561 #size-cells = <0>;
567 compatible = "ti,am3359-tscadc";
570 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
572 assigned-clocks = <&k3_clks 0 3>;
573 assigned-clock-rates = <60000000>;
574 clock-names = "fck";
577 dma-names = "fifo0", "fifo1";
580 #io-channel-cells = <1>;
581 compatible = "ti,am3359-adc";
586 compatible = "ti,j7200-r5fss";
587 ti,cluster-mode = <1>;
588 #address-cells = <1>;
589 #size-cells = <1>;
592 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
595 compatible = "ti,j7200-r5f";
598 reg-names = "atcm", "btcm";
599 ti,sci = <&dmsc>;
600 ti,sci-dev-id = <250>;
601 ti,sci-proc-ids = <0x01 0xff>;
603 firmware-name = "j7200-mcu-r5f0_0-fw";
604 ti,atcm-enable = <1>;
605 ti,btcm-enable = <1>;
610 compatible = "ti,j7200-r5f";
613 reg-names = "atcm", "btcm";
614 ti,sci = <&dmsc>;
615 ti,sci-dev-id = <251>;
616 ti,sci-proc-ids = <0x02 0xff>;
618 firmware-name = "j7200-mcu-r5f0_1-fw";
619 ti,atcm-enable = <1>;
620 ti,btcm-enable = <1>;
626 compatible = "ti,j721e-sa2ul";
628 power-domains = <&k3_pds 265 TI_SCI_PD_SHARED>;
629 #address-cells = <2>;
630 #size-cells = <2>;
634 dma-names = "tx", "rx1", "rx2";
637 compatible = "inside-secure,safexcel-eip76";
640 status = "disabled"; /* Used by OP-TEE */
644 wkup_vtm0: temperature-sensor@42040000 {
645 compatible = "ti,j7200-vtm";
648 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
649 #thermal-sensor-cells = <1>;
653 compatible = "ti,j721e-esm";
655 ti,esm-pins = <95>;
656 bootph-pre-ram;