Lines Matching +full:i2c +full:- +full:alias
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3568-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3568-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
49 #address-cells = <2>;
50 #size-cells = <0>;
54 compatible = "arm,cortex-a55";
57 #cooling-cells = <2>;
58 enable-method = "psci";
59 i-cache-size = <0x8000>;
60 i-cache-line-size = <64>;
61 i-cache-sets = <128>;
62 d-cache-size = <0x8000>;
63 d-cache-line-size = <64>;
64 d-cache-sets = <128>;
65 next-level-cache = <&l3_cache>;
70 compatible = "arm,cortex-a55";
72 #cooling-cells = <2>;
73 enable-method = "psci";
74 i-cache-size = <0x8000>;
75 i-cache-line-size = <64>;
76 i-cache-sets = <128>;
77 d-cache-size = <0x8000>;
78 d-cache-line-size = <64>;
79 d-cache-sets = <128>;
80 next-level-cache = <&l3_cache>;
85 compatible = "arm,cortex-a55";
87 #cooling-cells = <2>;
88 enable-method = "psci";
89 i-cache-size = <0x8000>;
90 i-cache-line-size = <64>;
91 i-cache-sets = <128>;
92 d-cache-size = <0x8000>;
93 d-cache-line-size = <64>;
94 d-cache-sets = <128>;
95 next-level-cache = <&l3_cache>;
100 compatible = "arm,cortex-a55";
102 #cooling-cells = <2>;
103 enable-method = "psci";
104 i-cache-size = <0x8000>;
105 i-cache-line-size = <64>;
106 i-cache-sets = <128>;
107 d-cache-size = <0x8000>;
108 d-cache-line-size = <64>;
109 d-cache-sets = <128>;
110 next-level-cache = <&l3_cache>;
115 * There are no private per-core L2 caches, but only the
118 l3_cache: l3-cache {
120 cache-level = <2>;
121 cache-unified;
122 cache-size = <0x80000>;
123 cache-line-size = <64>;
124 cache-sets = <512>;
127 display_subsystem: display-subsystem {
128 compatible = "rockchip,display-subsystem";
134 compatible = "arm,scmi-smc";
135 arm,smc-id = <0x82000010>;
137 #address-cells = <1>;
138 #size-cells = <0>;
142 #clock-cells = <1>;
147 hdmi_sound: hdmi-sound {
148 compatible = "simple-audio-card";
149 simple-audio-card,name = "HDMI";
150 simple-audio-card,format = "i2s";
151 simple-audio-card,mclk-fs = <256>;
154 simple-audio-card,codec {
155 sound-dai = <&hdmi>;
158 simple-audio-card,cpu {
159 sound-dai = <&i2s0_8ch>;
164 compatible = "arm,cortex-a55-pmu";
169 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
173 compatible = "arm,psci-1.0";
177 reserved-memory {
178 #address-cells = <2>;
179 #size-cells = <2>;
183 compatible = "arm,scmi-shmem";
185 no-map;
190 compatible = "arm,armv8-timer";
195 arm,no-tick-in-suspend;
199 compatible = "fixed-clock";
200 clock-frequency = <24000000>;
201 clock-output-names = "xin24m";
202 #clock-cells = <0>;
206 compatible = "fixed-clock";
207 clock-frequency = <32768>;
208 clock-output-names = "xin32k";
209 pinctrl-0 = <&clk32k_out0>;
210 pinctrl-names = "default";
211 #clock-cells = <0>;
215 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
219 clock-names = "sata", "pmalive", "rxoob";
222 phy-names = "sata-phy";
223 ports-implemented = <0x1>;
224 power-domains = <&power RK3568_PD_PIPE>;
229 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
233 clock-names = "sata", "pmalive", "rxoob";
236 phy-names = "sata-phy";
237 ports-implemented = <0x1>;
238 power-domains = <&power RK3568_PD_PIPE>;
243 compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
248 clock-names = "ref_clk", "suspend_clk",
252 power-domains = <&power RK3568_PD_PIPE>;
259 compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
264 clock-names = "ref_clk", "suspend_clk",
268 phy-names = "usb2-phy", "usb3-phy";
270 power-domains = <&power RK3568_PD_PIPE>;
276 gic: interrupt-controller@fd400000 {
277 compatible = "arm,gic-v3";
281 interrupt-controller;
282 #interrupt-cells = <3>;
283 mbi-alias = <0x0 0xfd410000>;
284 mbi-ranges = <296 24>;
285 msi-controller;
289 compatible = "generic-ehci";
295 phy-names = "usb";
300 compatible = "generic-ohci";
306 phy-names = "usb";
311 compatible = "generic-ehci";
317 phy-names = "usb";
322 compatible = "generic-ohci";
328 phy-names = "usb";
333 compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
336 pmu_io_domains: io-domains {
337 compatible = "rockchip,rk3568-pmu-io-voltage-domain";
347 compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
352 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
357 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
362 compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
367 compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
371 pmucru: clock-controller@fdd00000 {
372 compatible = "rockchip,rk3568-pmucru";
374 #clock-cells = <1>;
375 #reset-cells = <1>;
378 cru: clock-controller@fdd20000 {
379 compatible = "rockchip,rk3568-cru";
382 clock-names = "xin24m";
383 #clock-cells = <1>;
384 #reset-cells = <1>;
385 assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
386 assigned-clock-rates = <32768>, <1200000000>, <200000000>;
387 assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>;
391 i2c0: i2c@fdd40000 {
392 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
396 clock-names = "i2c", "pclk";
397 pinctrl-0 = <&i2c0_xfer>;
398 pinctrl-names = "default";
399 #address-cells = <1>;
400 #size-cells = <0>;
405 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
409 clock-names = "baudclk", "apb_pclk";
411 pinctrl-0 = <&uart0_xfer>;
412 pinctrl-names = "default";
413 reg-io-width = <4>;
414 reg-shift = <2>;
419 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
422 clock-names = "pwm", "pclk";
423 pinctrl-0 = <&pwm0m0_pins>;
424 pinctrl-names = "default";
425 #pwm-cells = <3>;
430 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
433 clock-names = "pwm", "pclk";
434 pinctrl-0 = <&pwm1m0_pins>;
435 pinctrl-names = "default";
436 #pwm-cells = <3>;
441 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
444 clock-names = "pwm", "pclk";
445 pinctrl-0 = <&pwm2m0_pins>;
446 pinctrl-names = "default";
447 #pwm-cells = <3>;
452 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
455 clock-names = "pwm", "pclk";
456 pinctrl-0 = <&pwm3_pins>;
457 pinctrl-names = "default";
458 #pwm-cells = <3>;
462 pmu: power-management@fdd90000 {
463 compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd";
466 power: power-controller {
467 compatible = "rockchip,rk3568-power-controller";
468 #power-domain-cells = <1>;
469 #address-cells = <1>;
470 #size-cells = <0>;
473 power-domain@RK3568_PD_GPU {
478 #power-domain-cells = <0>;
482 power-domain@RK3568_PD_VI {
489 #power-domain-cells = <0>;
492 power-domain@RK3568_PD_VO {
500 #power-domain-cells = <0>;
503 power-domain@RK3568_PD_RGA {
513 #power-domain-cells = <0>;
516 power-domain@RK3568_PD_VPU {
520 #power-domain-cells = <0>;
523 power-domain@RK3568_PD_RKVDEC {
527 #power-domain-cells = <0>;
530 power-domain@RK3568_PD_RKVENC {
536 #power-domain-cells = <0>;
542 compatible = "rockchip,rk3568-mali", "arm,mali-bifrost";
547 interrupt-names = "job", "mmu", "gpu";
549 clock-names = "gpu", "bus";
550 #cooling-cells = <2>;
551 power-domains = <&power RK3568_PD_GPU>;
555 vpu: video-codec@fdea0400 {
556 compatible = "rockchip,rk3568-vpu";
559 interrupt-names = "vdpu";
561 clock-names = "aclk", "hclk";
563 power-domains = <&power RK3568_PD_VPU>;
567 compatible = "rockchip,rk3568-iommu";
570 clock-names = "aclk", "iface";
572 power-domains = <&power RK3568_PD_VPU>;
573 #iommu-cells = <0>;
577 compatible = "rockchip,rk3568-rga", "rockchip,rk3288-rga";
581 clock-names = "aclk", "hclk", "sclk";
583 reset-names = "core", "axi", "ahb";
584 power-domains = <&power RK3568_PD_RGA>;
587 vepu: video-codec@fdee0000 {
588 compatible = "rockchip,rk3568-vepu";
592 clock-names = "aclk", "hclk";
594 power-domains = <&power RK3568_PD_RGA>;
598 compatible = "rockchip,rk3568-iommu";
602 clock-names = "aclk", "iface";
603 power-domains = <&power RK3568_PD_RGA>;
604 #iommu-cells = <0>;
608 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
613 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
614 fifo-depth = <0x100>;
615 max-frequency = <150000000>;
617 reset-names = "reset";
622 compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
626 interrupt-names = "macirq", "eth_wake_irq";
631 clock-names = "stmmaceth", "mac_clk_rx",
636 reset-names = "stmmaceth";
638 snps,axi-config = <&gmac1_stmmac_axi_setup>;
639 snps,mixed-burst;
640 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
641 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
646 compatible = "snps,dwmac-mdio";
647 #address-cells = <0x1>;
648 #size-cells = <0x0>;
651 gmac1_stmmac_axi_setup: stmmac-axi-config {
657 gmac1_mtl_rx_setup: rx-queues-config {
658 snps,rx-queues-to-use = <1>;
662 gmac1_mtl_tx_setup: tx-queues-config {
663 snps,tx-queues-to-use = <1>;
670 reg-names = "vop", "gamma-lut";
674 clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2";
676 power-domains = <&power RK3568_PD_VO>;
681 #address-cells = <1>;
682 #size-cells = <0>;
686 #address-cells = <1>;
687 #size-cells = <0>;
692 #address-cells = <1>;
693 #size-cells = <0>;
698 #address-cells = <1>;
699 #size-cells = <0>;
705 compatible = "rockchip,rk3568-iommu";
709 clock-names = "aclk", "iface";
710 #iommu-cells = <0>;
711 power-domains = <&power RK3568_PD_VO>;
716 compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
719 clock-names = "pclk";
721 phy-names = "dphy";
723 power-domains = <&power RK3568_PD_VO>;
724 reset-names = "apb";
730 #address-cells = <1>;
731 #size-cells = <0>;
744 compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
747 clock-names = "pclk";
749 phy-names = "dphy";
751 power-domains = <&power RK3568_PD_VO>;
752 reset-names = "apb";
758 #address-cells = <1>;
759 #size-cells = <0>;
772 compatible = "rockchip,rk3568-dw-hdmi";
780 clock-names = "iahb", "isfr", "cec", "ref";
781 pinctrl-names = "default";
782 pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>;
783 power-domains = <&power RK3568_PD_VO>;
784 reg-io-width = <4>;
786 #sound-dai-cells = <0>;
790 #address-cells = <1>;
791 #size-cells = <0>;
804 compatible = "rockchip,rk3568-qos", "syscon";
809 compatible = "rockchip,rk3568-qos", "syscon";
814 compatible = "rockchip,rk3568-qos", "syscon";
819 compatible = "rockchip,rk3568-qos", "syscon";
824 compatible = "rockchip,rk3568-qos", "syscon";
829 compatible = "rockchip,rk3568-qos", "syscon";
834 compatible = "rockchip,rk3568-qos", "syscon";
839 compatible = "rockchip,rk3568-qos", "syscon";
844 compatible = "rockchip,rk3568-qos", "syscon";
849 compatible = "rockchip,rk3568-qos", "syscon";
854 compatible = "rockchip,rk3568-qos", "syscon";
859 compatible = "rockchip,rk3568-qos", "syscon";
864 compatible = "rockchip,rk3568-qos", "syscon";
869 compatible = "rockchip,rk3568-qos", "syscon";
874 compatible = "rockchip,rk3568-qos", "syscon";
879 compatible = "rockchip,rk3568-qos", "syscon";
884 compatible = "rockchip,rk3568-qos", "syscon";
889 compatible = "rockchip,rk3568-qos", "syscon";
894 compatible = "rockchip,rk3568-qos", "syscon";
899 compatible = "rockchip,rk3568-qos", "syscon";
904 compatible = "rockchip,rk3568-qos", "syscon";
909 compatible = "rockchip,rk3568-qos", "syscon";
914 compatible = "rockchip,rk3568-qos", "syscon";
919 compatible = "rockchip,rk3568-qos", "syscon";
924 compatible = "rockchip,rk3568-dfi";
931 compatible = "rockchip,rk3568-pcie";
935 reg-names = "dbi", "apb", "config";
941 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
942 bus-range = <0x0 0xf>;
946 clock-names = "aclk_mst", "aclk_slv",
949 #interrupt-cells = <1>;
950 interrupt-map-mask = <0 0 0 7>;
951 interrupt-map = <0 0 0 1 &pcie_intc 0>,
955 linux,pci-domain = <0>;
956 num-ib-windows = <6>;
957 num-ob-windows = <2>;
958 max-link-speed = <2>;
959 msi-map = <0x0 &gic 0x0 0x1000>;
960 num-lanes = <1>;
962 phy-names = "pcie-phy";
963 power-domains = <&power RK3568_PD_PIPE>;
968 reset-names = "pipe";
969 #address-cells = <3>;
970 #size-cells = <2>;
973 pcie_intc: legacy-interrupt-controller {
974 #address-cells = <0>;
975 #interrupt-cells = <1>;
976 interrupt-controller;
977 interrupt-parent = <&gic>;
983 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
988 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
989 fifo-depth = <0x100>;
990 max-frequency = <150000000>;
992 reset-names = "reset";
997 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
1002 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1003 fifo-depth = <0x100>;
1004 max-frequency = <150000000>;
1006 reset-names = "reset";
1015 clock-names = "clk_sfc", "hclk_sfc";
1016 pinctrl-0 = <&fspi_pins>;
1017 pinctrl-names = "default";
1022 compatible = "rockchip,rk3568-dwcmshc";
1025 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>;
1026 assigned-clock-rates = <200000000>, <24000000>;
1030 clock-names = "core", "bus", "axi", "block", "timer";
1040 compatible = "rockchip,rk3568-rng";
1043 clock-names = "core", "ahb";
1049 compatible = "rockchip,rk3568-i2s-tdm";
1052 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
1053 assigned-clock-rates = <1188000000>, <1188000000>;
1055 clock-names = "mclk_tx", "mclk_rx", "hclk";
1057 dma-names = "tx";
1059 reset-names = "tx-m", "rx-m";
1061 #sound-dai-cells = <0>;
1066 compatible = "rockchip,rk3568-i2s-tdm";
1069 assigned-clocks = <&cru CLK_I2S1_8CH_TX_SRC>, <&cru CLK_I2S1_8CH_RX_SRC>;
1070 assigned-clock-rates = <1188000000>, <1188000000>;
1073 clock-names = "mclk_tx", "mclk_rx", "hclk";
1075 dma-names = "rx", "tx";
1077 reset-names = "tx-m", "rx-m";
1079 pinctrl-names = "default";
1080 pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx
1086 #sound-dai-cells = <0>;
1091 compatible = "rockchip,rk3568-i2s-tdm";
1094 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
1095 assigned-clock-rates = <1188000000>;
1097 clock-names = "mclk_tx", "mclk_rx", "hclk";
1099 dma-names = "tx", "rx";
1101 reset-names = "tx-m";
1103 pinctrl-names = "default";
1104 pinctrl-0 = <&i2s2m0_sclktx
1108 #sound-dai-cells = <0>;
1113 compatible = "rockchip,rk3568-i2s-tdm";
1118 clock-names = "mclk_tx", "mclk_rx", "hclk";
1120 dma-names = "tx", "rx";
1122 reset-names = "tx-m", "rx-m";
1124 #sound-dai-cells = <0>;
1129 compatible = "rockchip,rk3568-pdm";
1133 clock-names = "pdm_clk", "pdm_hclk";
1135 dma-names = "rx";
1136 pinctrl-0 = <&pdmm0_clk
1142 pinctrl-names = "default";
1144 reset-names = "pdm-m";
1145 #sound-dai-cells = <0>;
1150 compatible = "rockchip,rk3568-spdif";
1153 clock-names = "mclk", "hclk";
1156 dma-names = "tx";
1157 pinctrl-names = "default";
1158 pinctrl-0 = <&spdifm0_tx>;
1159 #sound-dai-cells = <0>;
1163 dmac0: dma-controller@fe530000 {
1168 arm,pl330-periph-burst;
1170 clock-names = "apb_pclk";
1171 #dma-cells = <1>;
1174 dmac1: dma-controller@fe550000 {
1179 arm,pl330-periph-burst;
1181 clock-names = "apb_pclk";
1182 #dma-cells = <1>;
1185 i2c1: i2c@fe5a0000 {
1186 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1190 clock-names = "i2c", "pclk";
1191 pinctrl-0 = <&i2c1_xfer>;
1192 pinctrl-names = "default";
1193 #address-cells = <1>;
1194 #size-cells = <0>;
1198 i2c2: i2c@fe5b0000 {
1199 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1203 clock-names = "i2c", "pclk";
1204 pinctrl-0 = <&i2c2m0_xfer>;
1205 pinctrl-names = "default";
1206 #address-cells = <1>;
1207 #size-cells = <0>;
1211 i2c3: i2c@fe5c0000 {
1212 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1216 clock-names = "i2c", "pclk";
1217 pinctrl-0 = <&i2c3m0_xfer>;
1218 pinctrl-names = "default";
1219 #address-cells = <1>;
1220 #size-cells = <0>;
1224 i2c4: i2c@fe5d0000 {
1225 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1229 clock-names = "i2c", "pclk";
1230 pinctrl-0 = <&i2c4m0_xfer>;
1231 pinctrl-names = "default";
1232 #address-cells = <1>;
1233 #size-cells = <0>;
1237 i2c5: i2c@fe5e0000 {
1238 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1242 clock-names = "i2c", "pclk";
1243 pinctrl-0 = <&i2c5m0_xfer>;
1244 pinctrl-names = "default";
1245 #address-cells = <1>;
1246 #size-cells = <0>;
1251 compatible = "rockchip,rk3568-wdt", "snps,dw-wdt";
1255 clock-names = "tclk", "pclk";
1259 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1263 clock-names = "spiclk", "apb_pclk";
1265 dma-names = "tx", "rx";
1266 pinctrl-names = "default";
1267 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
1268 #address-cells = <1>;
1269 #size-cells = <0>;
1274 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1278 clock-names = "spiclk", "apb_pclk";
1280 dma-names = "tx", "rx";
1281 pinctrl-names = "default";
1282 pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>;
1283 #address-cells = <1>;
1284 #size-cells = <0>;
1289 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1293 clock-names = "spiclk", "apb_pclk";
1295 dma-names = "tx", "rx";
1296 pinctrl-names = "default";
1297 pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>;
1298 #address-cells = <1>;
1299 #size-cells = <0>;
1304 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1308 clock-names = "spiclk", "apb_pclk";
1310 dma-names = "tx", "rx";
1311 pinctrl-names = "default";
1312 pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>;
1313 #address-cells = <1>;
1314 #size-cells = <0>;
1319 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1323 clock-names = "baudclk", "apb_pclk";
1325 pinctrl-0 = <&uart1m0_xfer>;
1326 pinctrl-names = "default";
1327 reg-io-width = <4>;
1328 reg-shift = <2>;
1333 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1337 clock-names = "baudclk", "apb_pclk";
1339 pinctrl-0 = <&uart2m0_xfer>;
1340 pinctrl-names = "default";
1341 reg-io-width = <4>;
1342 reg-shift = <2>;
1347 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1351 clock-names = "baudclk", "apb_pclk";
1353 pinctrl-0 = <&uart3m0_xfer>;
1354 pinctrl-names = "default";
1355 reg-io-width = <4>;
1356 reg-shift = <2>;
1361 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1365 clock-names = "baudclk", "apb_pclk";
1367 pinctrl-0 = <&uart4m0_xfer>;
1368 pinctrl-names = "default";
1369 reg-io-width = <4>;
1370 reg-shift = <2>;
1375 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1379 clock-names = "baudclk", "apb_pclk";
1381 pinctrl-0 = <&uart5m0_xfer>;
1382 pinctrl-names = "default";
1383 reg-io-width = <4>;
1384 reg-shift = <2>;
1389 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1393 clock-names = "baudclk", "apb_pclk";
1395 pinctrl-0 = <&uart6m0_xfer>;
1396 pinctrl-names = "default";
1397 reg-io-width = <4>;
1398 reg-shift = <2>;
1403 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1407 clock-names = "baudclk", "apb_pclk";
1409 pinctrl-0 = <&uart7m0_xfer>;
1410 pinctrl-names = "default";
1411 reg-io-width = <4>;
1412 reg-shift = <2>;
1417 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1421 clock-names = "baudclk", "apb_pclk";
1423 pinctrl-0 = <&uart8m0_xfer>;
1424 pinctrl-names = "default";
1425 reg-io-width = <4>;
1426 reg-shift = <2>;
1431 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1435 clock-names = "baudclk", "apb_pclk";
1437 pinctrl-0 = <&uart9m0_xfer>;
1438 pinctrl-names = "default";
1439 reg-io-width = <4>;
1440 reg-shift = <2>;
1444 thermal_zones: thermal-zones {
1445 cpu_thermal: cpu-thermal {
1446 polling-delay-passive = <100>;
1447 polling-delay = <1000>;
1449 thermal-sensors = <&tsadc 0>;
1469 cooling-maps {
1472 cooling-device =
1481 gpu_thermal: gpu-thermal {
1482 polling-delay-passive = <20>; /* milliseconds */
1483 polling-delay = <1000>; /* milliseconds */
1485 thermal-sensors = <&tsadc 1>;
1488 gpu_threshold: gpu-threshold {
1493 gpu_target: gpu-target {
1498 gpu_crit: gpu-crit {
1505 cooling-maps {
1508 cooling-device =
1516 compatible = "rockchip,rk3568-tsadc";
1519 assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>;
1520 assigned-clock-rates = <17000000>, <700000>;
1522 clock-names = "tsadc", "apb_pclk";
1526 rockchip,hw-tshut-temp = <95000>;
1527 pinctrl-names = "default", "sleep";
1528 pinctrl-0 = <&tsadc_shutorg>;
1529 pinctrl-1 = <&tsadc_pin>;
1530 #thermal-sensor-cells = <1>;
1535 compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc";
1539 clock-names = "saradc", "apb_pclk";
1541 reset-names = "saradc-apb";
1542 #io-channel-cells = <1>;
1547 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1550 clock-names = "pwm", "pclk";
1551 pinctrl-0 = <&pwm4_pins>;
1552 pinctrl-names = "default";
1553 #pwm-cells = <3>;
1558 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1561 clock-names = "pwm", "pclk";
1562 pinctrl-0 = <&pwm5_pins>;
1563 pinctrl-names = "default";
1564 #pwm-cells = <3>;
1569 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1572 clock-names = "pwm", "pclk";
1573 pinctrl-0 = <&pwm6_pins>;
1574 pinctrl-names = "default";
1575 #pwm-cells = <3>;
1580 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1583 clock-names = "pwm", "pclk";
1584 pinctrl-0 = <&pwm7_pins>;
1585 pinctrl-names = "default";
1586 #pwm-cells = <3>;
1591 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1594 clock-names = "pwm", "pclk";
1595 pinctrl-0 = <&pwm8m0_pins>;
1596 pinctrl-names = "default";
1597 #pwm-cells = <3>;
1602 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1605 clock-names = "pwm", "pclk";
1606 pinctrl-0 = <&pwm9m0_pins>;
1607 pinctrl-names = "default";
1608 #pwm-cells = <3>;
1613 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1616 clock-names = "pwm", "pclk";
1617 pinctrl-0 = <&pwm10m0_pins>;
1618 pinctrl-names = "default";
1619 #pwm-cells = <3>;
1624 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1627 clock-names = "pwm", "pclk";
1628 pinctrl-0 = <&pwm11m0_pins>;
1629 pinctrl-names = "default";
1630 #pwm-cells = <3>;
1635 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1638 clock-names = "pwm", "pclk";
1639 pinctrl-0 = <&pwm12m0_pins>;
1640 pinctrl-names = "default";
1641 #pwm-cells = <3>;
1646 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1649 clock-names = "pwm", "pclk";
1650 pinctrl-0 = <&pwm13m0_pins>;
1651 pinctrl-names = "default";
1652 #pwm-cells = <3>;
1657 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1660 clock-names = "pwm", "pclk";
1661 pinctrl-0 = <&pwm14m0_pins>;
1662 pinctrl-names = "default";
1663 #pwm-cells = <3>;
1668 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1671 clock-names = "pwm", "pclk";
1672 pinctrl-0 = <&pwm15m0_pins>;
1673 pinctrl-names = "default";
1674 #pwm-cells = <3>;
1679 compatible = "rockchip,rk3568-naneng-combphy";
1684 clock-names = "ref", "apb", "pipe";
1685 assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
1686 assigned-clock-rates = <100000000>;
1688 reset-names = "phy";
1689 rockchip,pipe-grf = <&pipegrf>;
1690 rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
1691 #phy-cells = <1>;
1696 compatible = "rockchip,rk3568-naneng-combphy";
1701 clock-names = "ref", "apb", "pipe";
1702 assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
1703 assigned-clock-rates = <100000000>;
1705 reset-names = "phy";
1706 rockchip,pipe-grf = <&pipegrf>;
1707 rockchip,pipe-phy-grf = <&pipe_phy_grf2>;
1708 #phy-cells = <1>;
1713 compatible = "rockchip,rk3568-csi-dphy";
1716 clock-names = "pclk";
1717 #phy-cells = <0>;
1719 reset-names = "apb";
1724 dsi_dphy0: mipi-dphy@fe850000 {
1725 compatible = "rockchip,rk3568-dsi-dphy";
1727 clock-names = "ref", "pclk";
1729 #phy-cells = <0>;
1730 power-domains = <&power RK3568_PD_VO>;
1731 reset-names = "apb";
1736 dsi_dphy1: mipi-dphy@fe860000 {
1737 compatible = "rockchip,rk3568-dsi-dphy";
1739 clock-names = "ref", "pclk";
1741 #phy-cells = <0>;
1742 power-domains = <&power RK3568_PD_VO>;
1743 reset-names = "apb";
1749 compatible = "rockchip,rk3568-usb2phy";
1752 clock-names = "phyclk";
1753 clock-output-names = "clk_usbphy0_480m";
1756 #clock-cells = <0>;
1759 usb2phy0_host: host-port {
1760 #phy-cells = <0>;
1764 usb2phy0_otg: otg-port {
1765 #phy-cells = <0>;
1771 compatible = "rockchip,rk3568-usb2phy";
1774 clock-names = "phyclk";
1775 clock-output-names = "clk_usbphy1_480m";
1778 #clock-cells = <0>;
1781 usb2phy1_host: host-port {
1782 #phy-cells = <0>;
1786 usb2phy1_otg: otg-port {
1787 #phy-cells = <0>;
1793 compatible = "rockchip,rk3568-pinctrl";
1796 #address-cells = <2>;
1797 #size-cells = <2>;
1801 compatible = "rockchip,gpio-bank";
1805 gpio-controller;
1806 gpio-ranges = <&pinctrl 0 0 32>;
1807 #gpio-cells = <2>;
1808 interrupt-controller;
1809 #interrupt-cells = <2>;
1813 compatible = "rockchip,gpio-bank";
1817 gpio-controller;
1818 gpio-ranges = <&pinctrl 0 32 32>;
1819 #gpio-cells = <2>;
1820 interrupt-controller;
1821 #interrupt-cells = <2>;
1825 compatible = "rockchip,gpio-bank";
1829 gpio-controller;
1830 gpio-ranges = <&pinctrl 0 64 32>;
1831 #gpio-cells = <2>;
1832 interrupt-controller;
1833 #interrupt-cells = <2>;
1837 compatible = "rockchip,gpio-bank";
1841 gpio-controller;
1842 gpio-ranges = <&pinctrl 0 96 32>;
1843 #gpio-cells = <2>;
1844 interrupt-controller;
1845 #interrupt-cells = <2>;
1849 compatible = "rockchip,gpio-bank";
1853 gpio-controller;
1854 gpio-ranges = <&pinctrl 0 128 32>;
1855 #gpio-cells = <2>;
1856 interrupt-controller;
1857 #interrupt-cells = <2>;
1862 #include "rk3568-pinctrl.dtsi"