Lines Matching +full:rk3399 +full:- +full:pmucru
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/px30-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/px30-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
38 #address-cells = <2>;
39 #size-cells = <0>;
43 compatible = "arm,cortex-a35";
45 enable-method = "psci";
47 #cooling-cells = <2>;
48 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
49 dynamic-power-coefficient = <90>;
50 operating-points-v2 = <&cpu0_opp_table>;
55 compatible = "arm,cortex-a35";
57 enable-method = "psci";
59 #cooling-cells = <2>;
60 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
61 dynamic-power-coefficient = <90>;
62 operating-points-v2 = <&cpu0_opp_table>;
67 compatible = "arm,cortex-a35";
69 enable-method = "psci";
71 #cooling-cells = <2>;
72 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
73 dynamic-power-coefficient = <90>;
74 operating-points-v2 = <&cpu0_opp_table>;
79 compatible = "arm,cortex-a35";
81 enable-method = "psci";
83 #cooling-cells = <2>;
84 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
85 dynamic-power-coefficient = <90>;
86 operating-points-v2 = <&cpu0_opp_table>;
89 idle-states {
90 entry-method = "psci";
92 CPU_SLEEP: cpu-sleep {
93 compatible = "arm,idle-state";
94 local-timer-stop;
95 arm,psci-suspend-param = <0x0010000>;
96 entry-latency-us = <120>;
97 exit-latency-us = <250>;
98 min-residency-us = <900>;
101 CLUSTER_SLEEP: cluster-sleep {
102 compatible = "arm,idle-state";
103 local-timer-stop;
104 arm,psci-suspend-param = <0x1010000>;
105 entry-latency-us = <400>;
106 exit-latency-us = <500>;
107 min-residency-us = <2000>;
112 cpu0_opp_table: opp-table-0 {
113 compatible = "operating-points-v2";
114 opp-shared;
116 opp-600000000 {
117 opp-hz = /bits/ 64 <600000000>;
118 opp-microvolt = <950000 950000 1350000>;
119 clock-latency-ns = <40000>;
120 opp-suspend;
122 opp-816000000 {
123 opp-hz = /bits/ 64 <816000000>;
124 opp-microvolt = <1050000 1050000 1350000>;
125 clock-latency-ns = <40000>;
127 opp-1008000000 {
128 opp-hz = /bits/ 64 <1008000000>;
129 opp-microvolt = <1175000 1175000 1350000>;
130 clock-latency-ns = <40000>;
132 opp-1200000000 {
133 opp-hz = /bits/ 64 <1200000000>;
134 opp-microvolt = <1300000 1300000 1350000>;
135 clock-latency-ns = <40000>;
137 opp-1296000000 {
138 opp-hz = /bits/ 64 <1296000000>;
139 opp-microvolt = <1350000 1350000 1350000>;
140 clock-latency-ns = <40000>;
144 arm-pmu {
145 compatible = "arm,cortex-a35-pmu";
150 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
153 display_subsystem: display-subsystem {
154 compatible = "rockchip,display-subsystem";
159 gmac_clkin: external-gmac-clock {
160 compatible = "fixed-clock";
161 clock-frequency = <50000000>;
162 clock-output-names = "gmac_clkin";
163 #clock-cells = <0>;
167 compatible = "arm,psci-1.0";
172 compatible = "arm,armv8-timer";
179 thermal_zones: thermal-zones {
180 soc_thermal: soc-thermal {
181 polling-delay-passive = <20>;
182 polling-delay = <1000>;
183 sustainable-power = <750>;
184 thermal-sensors = <&tsadc 0>;
187 threshold: trip-point-0 {
193 target: trip-point-1 {
199 soc_crit: soc-crit {
206 cooling-maps {
209 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
215 gpu_thermal: gpu-thermal {
216 polling-delay-passive = <100>; /* milliseconds */
217 polling-delay = <1000>; /* milliseconds */
218 thermal-sensors = <&tsadc 1>;
221 gpu_threshold: gpu-threshold {
227 gpu_target: gpu-target {
233 gpu_crit: gpu-crit {
240 cooling-maps {
243 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
250 compatible = "fixed-clock";
251 #clock-cells = <0>;
252 clock-frequency = <24000000>;
253 clock-output-names = "xin24m";
256 pmu: power-management@ff000000 {
257 compatible = "rockchip,px30-pmu", "syscon", "simple-mfd";
260 power: power-controller {
261 compatible = "rockchip,px30-power-controller";
262 #power-domain-cells = <1>;
263 #address-cells = <1>;
264 #size-cells = <0>;
267 power-domain@PX30_PD_USB {
273 #power-domain-cells = <0>;
275 power-domain@PX30_PD_SDCARD {
280 #power-domain-cells = <0>;
282 power-domain@PX30_PD_GMAC {
289 #power-domain-cells = <0>;
291 power-domain@PX30_PD_MMC_NAND {
303 #power-domain-cells = <0>;
305 power-domain@PX30_PD_VPU {
311 #power-domain-cells = <0>;
313 power-domain@PX30_PD_VO {
328 #power-domain-cells = <0>;
330 power-domain@PX30_PD_VI {
340 #power-domain-cells = <0>;
342 power-domain@PX30_PD_GPU {
346 #power-domain-cells = <0>;
352 compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd";
354 #address-cells = <1>;
355 #size-cells = <1>;
357 pmu_io_domains: io-domains {
358 compatible = "rockchip,px30-pmu-io-voltage-domain";
362 reboot-mode {
363 compatible = "syscon-reboot-mode";
365 mode-bootloader = <BOOT_BL_DOWNLOAD>;
366 mode-fastboot = <BOOT_FASTBOOT>;
367 mode-loader = <BOOT_BL_DOWNLOAD>;
368 mode-normal = <BOOT_NORMAL>;
369 mode-recovery = <BOOT_RECOVERY>;
374 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
377 clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;
378 clock-names = "baudclk", "apb_pclk";
380 dma-names = "tx", "rx";
381 reg-shift = <2>;
382 reg-io-width = <4>;
383 pinctrl-names = "default";
384 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
389 compatible = "rockchip,px30-i2s-tdm";
393 clock-names = "mclk_tx", "mclk_rx", "hclk";
395 dma-names = "tx", "rx";
398 reset-names = "tx-m", "rx-m";
399 pinctrl-names = "default";
400 pinctrl-0 = <&i2s0_8ch_sclktx &i2s0_8ch_sclkrx
406 #sound-dai-cells = <0>;
411 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
415 clock-names = "i2s_clk", "i2s_hclk";
417 dma-names = "tx", "rx";
418 pinctrl-names = "default";
419 pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck
421 #sound-dai-cells = <0>;
426 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
430 clock-names = "i2s_clk", "i2s_hclk";
432 dma-names = "tx", "rx";
433 pinctrl-names = "default";
434 pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck
436 #sound-dai-cells = <0>;
440 gic: interrupt-controller@ff131000 {
441 compatible = "arm,gic-400";
442 #interrupt-cells = <3>;
443 #address-cells = <0>;
444 interrupt-controller;
454 compatible = "rockchip,px30-grf", "syscon", "simple-mfd";
456 #address-cells = <1>;
457 #size-cells = <1>;
459 io_domains: io-domains {
460 compatible = "rockchip,px30-io-voltage-domain";
465 compatible = "rockchip,px30-lvds";
467 phy-names = "dphy";
473 #address-cells = <1>;
474 #size-cells = <0>;
478 #address-cells = <1>;
479 #size-cells = <0>;
483 remote-endpoint = <&vopb_out_lvds>;
488 remote-endpoint = <&vopl_out_lvds>;
500 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
504 clock-names = "baudclk", "apb_pclk";
506 dma-names = "tx", "rx";
507 reg-shift = <2>;
508 reg-io-width = <4>;
509 pinctrl-names = "default";
510 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
515 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
519 clock-names = "baudclk", "apb_pclk";
521 dma-names = "tx", "rx";
522 reg-shift = <2>;
523 reg-io-width = <4>;
524 pinctrl-names = "default";
525 pinctrl-0 = <&uart2m0_xfer>;
530 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
534 clock-names = "baudclk", "apb_pclk";
536 dma-names = "tx", "rx";
537 reg-shift = <2>;
538 reg-io-width = <4>;
539 pinctrl-names = "default";
540 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>;
545 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
549 clock-names = "baudclk", "apb_pclk";
551 dma-names = "tx", "rx";
552 reg-shift = <2>;
553 reg-io-width = <4>;
554 pinctrl-names = "default";
555 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
560 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
564 clock-names = "baudclk", "apb_pclk";
566 dma-names = "tx", "rx";
567 reg-shift = <2>;
568 reg-io-width = <4>;
569 pinctrl-names = "default";
570 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>;
575 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
578 clock-names = "i2c", "pclk";
580 pinctrl-names = "default";
581 pinctrl-0 = <&i2c0_xfer>;
582 #address-cells = <1>;
583 #size-cells = <0>;
588 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
591 clock-names = "i2c", "pclk";
593 pinctrl-names = "default";
594 pinctrl-0 = <&i2c1_xfer>;
595 #address-cells = <1>;
596 #size-cells = <0>;
601 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
604 clock-names = "i2c", "pclk";
606 pinctrl-names = "default";
607 pinctrl-0 = <&i2c2_xfer>;
608 #address-cells = <1>;
609 #size-cells = <0>;
614 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
617 clock-names = "i2c", "pclk";
619 pinctrl-names = "default";
620 pinctrl-0 = <&i2c3_xfer>;
621 #address-cells = <1>;
622 #size-cells = <0>;
627 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
631 clock-names = "spiclk", "apb_pclk";
633 dma-names = "tx", "rx";
634 num-cs = <2>;
635 pinctrl-names = "default";
636 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>;
637 #address-cells = <1>;
638 #size-cells = <0>;
643 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
647 clock-names = "spiclk", "apb_pclk";
649 dma-names = "tx", "rx";
650 num-cs = <2>;
651 pinctrl-names = "default";
652 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>;
653 #address-cells = <1>;
654 #size-cells = <0>;
659 compatible = "rockchip,px30-wdt", "snps,dw-wdt";
667 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
670 clock-names = "pwm", "pclk";
671 pinctrl-names = "default";
672 pinctrl-0 = <&pwm0_pin>;
673 #pwm-cells = <3>;
678 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
681 clock-names = "pwm", "pclk";
682 pinctrl-names = "default";
683 pinctrl-0 = <&pwm1_pin>;
684 #pwm-cells = <3>;
689 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
692 clock-names = "pwm", "pclk";
693 pinctrl-names = "default";
694 pinctrl-0 = <&pwm2_pin>;
695 #pwm-cells = <3>;
700 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
703 clock-names = "pwm", "pclk";
704 pinctrl-names = "default";
705 pinctrl-0 = <&pwm3_pin>;
706 #pwm-cells = <3>;
711 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
714 clock-names = "pwm", "pclk";
715 pinctrl-names = "default";
716 pinctrl-0 = <&pwm4_pin>;
717 #pwm-cells = <3>;
722 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
725 clock-names = "pwm", "pclk";
726 pinctrl-names = "default";
727 pinctrl-0 = <&pwm5_pin>;
728 #pwm-cells = <3>;
733 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
736 clock-names = "pwm", "pclk";
737 pinctrl-names = "default";
738 pinctrl-0 = <&pwm6_pin>;
739 #pwm-cells = <3>;
744 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
747 clock-names = "pwm", "pclk";
748 pinctrl-names = "default";
749 pinctrl-0 = <&pwm7_pin>;
750 #pwm-cells = <3>;
755 compatible = "rockchip,px30-timer", "rockchip,rk3288-timer";
759 clock-names = "pclk", "timer";
762 dmac: dma-controller@ff240000 {
767 arm,pl330-periph-burst;
769 clock-names = "apb_pclk";
770 #dma-cells = <1>;
774 compatible = "rockchip,px30-tsadc";
777 assigned-clocks = <&cru SCLK_TSADC>;
778 assigned-clock-rates = <50000>;
780 clock-names = "tsadc", "apb_pclk";
782 reset-names = "tsadc-apb";
784 rockchip,hw-tshut-temp = <120000>;
785 pinctrl-names = "init", "default", "sleep";
786 pinctrl-0 = <&tsadc_otp_pin>;
787 pinctrl-1 = <&tsadc_otp_out>;
788 pinctrl-2 = <&tsadc_otp_pin>;
789 #thermal-sensor-cells = <1>;
794 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc";
797 #io-channel-cells = <1>;
799 clock-names = "saradc", "apb_pclk";
801 reset-names = "saradc-apb";
806 compatible = "rockchip,px30-otp";
810 clock-names = "otp", "apb_pclk", "phy";
812 reset-names = "phy";
813 #address-cells = <1>;
814 #size-cells = <1>;
820 cpu_leakage: cpu-leakage@17 {
829 cru: clock-controller@ff2b0000 {
830 compatible = "rockchip,px30-cru";
832 clocks = <&xin24m>, <&pmucru PLL_GPLL>;
833 clock-names = "xin24m", "gpll";
835 #clock-cells = <1>;
836 #reset-cells = <1>;
838 assigned-clocks = <&cru PLL_NPLL>,
843 assigned-clock-rates = <1188000000>,
849 pmucru: clock-controller@ff2bc000 {
850 compatible = "rockchip,px30-pmucru";
853 clock-names = "xin24m";
855 #clock-cells = <1>;
856 #reset-cells = <1>;
858 assigned-clocks =
859 <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>,
860 <&pmucru SCLK_WIFI_PMU>;
861 assigned-clock-rates =
867 compatible = "rockchip,px30-usb2phy-grf", "syscon",
868 "simple-mfd";
870 #address-cells = <1>;
871 #size-cells = <1>;
874 compatible = "rockchip,px30-usb2phy";
876 clocks = <&pmucru SCLK_USBPHY_REF>;
877 clock-names = "phyclk";
878 #clock-cells = <0>;
879 assigned-clocks = <&cru USB480M>;
880 assigned-clock-parents = <&u2phy>;
881 clock-output-names = "usb480m_phy";
884 u2phy_host: host-port {
885 #phy-cells = <0>;
887 interrupt-names = "linestate";
891 u2phy_otg: otg-port {
892 #phy-cells = <0>;
896 interrupt-names = "otg-bvalid", "otg-id",
904 compatible = "rockchip,px30-dsi-dphy";
906 clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>;
907 clock-names = "ref", "pclk";
909 reset-names = "apb";
910 #phy-cells = <0>;
911 power-domains = <&power PX30_PD_VO>;
916 compatible = "rockchip,px30-csi-dphy";
919 clock-names = "pclk";
920 #phy-cells = <0>;
921 power-domains = <&power PX30_PD_VI>;
923 reset-names = "apb";
929 compatible = "rockchip,px30-usb", "rockchip,rk3066-usb",
934 clock-names = "otg";
936 g-np-tx-fifo-size = <16>;
937 g-rx-fifo-size = <280>;
938 g-tx-fifo-size = <256 128 128 64 32 16>;
940 phy-names = "usb2-phy";
941 power-domains = <&power PX30_PD_USB>;
946 compatible = "generic-ehci";
951 phy-names = "usb";
952 power-domains = <&power PX30_PD_USB>;
957 compatible = "generic-ohci";
962 phy-names = "usb";
963 power-domains = <&power PX30_PD_USB>;
968 compatible = "rockchip,px30-gmac";
971 interrupt-names = "macirq";
976 clock-names = "stmmaceth", "mac_clk_rx",
981 phy-mode = "rmii";
982 pinctrl-names = "default";
983 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
984 power-domains = <&power PX30_PD_GMAC>;
986 reset-names = "stmmaceth";
991 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
996 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
997 bus-width = <4>;
998 fifo-depth = <0x100>;
999 max-frequency = <150000000>;
1000 pinctrl-names = "default";
1001 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
1002 power-domains = <&power PX30_PD_SDCARD>;
1007 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
1012 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1013 bus-width = <4>;
1014 fifo-depth = <0x100>;
1015 max-frequency = <150000000>;
1016 pinctrl-names = "default";
1017 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
1018 power-domains = <&power PX30_PD_MMC_NAND>;
1023 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
1028 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1029 bus-width = <8>;
1030 fifo-depth = <0x100>;
1031 max-frequency = <150000000>;
1032 pinctrl-names = "default";
1033 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
1034 power-domains = <&power PX30_PD_MMC_NAND>;
1043 clock-names = "clk_sfc", "hclk_sfc";
1044 pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
1045 pinctrl-names = "default";
1046 power-domains = <&power PX30_PD_MMC_NAND>;
1050 nfc: nand-controller@ff3b0000 {
1051 compatible = "rockchip,px30-nfc";
1055 clock-names = "ahb", "nfc";
1056 assigned-clocks = <&cru SCLK_NANDC>;
1057 assigned-clock-rates = <150000000>;
1058 pinctrl-names = "default";
1059 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0
1061 power-domains = <&power PX30_PD_MMC_NAND>;
1065 gpu_opp_table: opp-table-1 {
1066 compatible = "operating-points-v2";
1068 opp-200000000 {
1069 opp-hz = /bits/ 64 <200000000>;
1070 opp-microvolt = <950000>;
1072 opp-300000000 {
1073 opp-hz = /bits/ 64 <300000000>;
1074 opp-microvolt = <975000>;
1076 opp-400000000 {
1077 opp-hz = /bits/ 64 <400000000>;
1078 opp-microvolt = <1050000>;
1080 opp-480000000 {
1081 opp-hz = /bits/ 64 <480000000>;
1082 opp-microvolt = <1125000>;
1087 compatible = "rockchip,px30-mali", "arm,mali-bifrost";
1092 interrupt-names = "job", "mmu", "gpu";
1094 #cooling-cells = <2>;
1095 power-domains = <&power PX30_PD_GPU>;
1096 operating-points-v2 = <&gpu_opp_table>;
1100 vpu: video-codec@ff442000 {
1101 compatible = "rockchip,px30-vpu";
1105 interrupt-names = "vepu", "vdpu";
1107 clock-names = "aclk", "hclk";
1109 power-domains = <&power PX30_PD_VPU>;
1117 clock-names = "aclk", "iface";
1118 #iommu-cells = <0>;
1119 power-domains = <&power PX30_PD_VPU>;
1123 compatible = "rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi";
1127 clock-names = "pclk";
1129 phy-names = "dphy";
1130 power-domains = <&power PX30_PD_VO>;
1132 reset-names = "apb";
1134 #address-cells = <1>;
1135 #size-cells = <0>;
1139 #address-cells = <1>;
1140 #size-cells = <0>;
1144 #address-cells = <1>;
1145 #size-cells = <0>;
1149 remote-endpoint = <&vopb_out_dsi>;
1154 remote-endpoint = <&vopl_out_dsi>;
1165 compatible = "rockchip,px30-vop-big";
1170 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1172 reset-names = "axi", "ahb", "dclk";
1174 power-domains = <&power PX30_PD_VO>;
1178 #address-cells = <1>;
1179 #size-cells = <0>;
1183 remote-endpoint = <&dsi_in_vopb>;
1188 remote-endpoint = <&lvds_vopb_in>;
1198 clock-names = "aclk", "iface";
1199 power-domains = <&power PX30_PD_VO>;
1200 #iommu-cells = <0>;
1205 compatible = "rockchip,px30-vop-lit";
1210 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1212 reset-names = "axi", "ahb", "dclk";
1214 power-domains = <&power PX30_PD_VO>;
1218 #address-cells = <1>;
1219 #size-cells = <0>;
1223 remote-endpoint = <&dsi_in_vopl>;
1228 remote-endpoint = <&lvds_vopl_in>;
1238 clock-names = "aclk", "iface";
1239 power-domains = <&power PX30_PD_VO>;
1240 #iommu-cells = <0>;
1245 compatible = "rockchip,px30-cif-isp"; /*rk3326-rkisp1*/
1250 interrupt-names = "isp", "mi", "mipi";
1255 clock-names = "isp", "aclk", "hclk", "pclk";
1258 phy-names = "dphy";
1259 power-domains = <&power PX30_PD_VI>;
1263 #address-cells = <1>;
1264 #size-cells = <0>;
1268 #address-cells = <1>;
1269 #size-cells = <0>;
1279 clock-names = "aclk", "iface";
1280 power-domains = <&power PX30_PD_VI>;
1281 rockchip,disable-mmu-reset;
1282 #iommu-cells = <0>;
1286 compatible = "rockchip,px30-qos", "syscon";
1291 compatible = "rockchip,px30-qos", "syscon";
1296 compatible = "rockchip,px30-qos", "syscon";
1301 compatible = "rockchip,px30-qos", "syscon";
1306 compatible = "rockchip,px30-qos", "syscon";
1311 compatible = "rockchip,px30-qos", "syscon";
1316 compatible = "rockchip,px30-qos", "syscon";
1321 compatible = "rockchip,px30-qos", "syscon";
1326 compatible = "rockchip,px30-qos", "syscon";
1331 compatible = "rockchip,px30-qos", "syscon";
1336 compatible = "rockchip,px30-qos", "syscon";
1341 compatible = "rockchip,px30-qos", "syscon";
1346 compatible = "rockchip,px30-qos", "syscon";
1351 compatible = "rockchip,px30-qos", "syscon";
1356 compatible = "rockchip,px30-qos", "syscon";
1361 compatible = "rockchip,px30-qos", "syscon";
1366 compatible = "rockchip,px30-qos", "syscon";
1371 compatible = "rockchip,px30-qos", "syscon";
1376 compatible = "rockchip,px30-qos", "syscon";
1381 compatible = "rockchip,px30-qos", "syscon";
1386 compatible = "rockchip,px30-pinctrl";
1389 #address-cells = <2>;
1390 #size-cells = <2>;
1394 compatible = "rockchip,gpio-bank";
1397 clocks = <&pmucru PCLK_GPIO0_PMU>;
1398 gpio-controller;
1399 #gpio-cells = <2>;
1401 interrupt-controller;
1402 #interrupt-cells = <2>;
1406 compatible = "rockchip,gpio-bank";
1410 gpio-controller;
1411 #gpio-cells = <2>;
1413 interrupt-controller;
1414 #interrupt-cells = <2>;
1418 compatible = "rockchip,gpio-bank";
1422 gpio-controller;
1423 #gpio-cells = <2>;
1425 interrupt-controller;
1426 #interrupt-cells = <2>;
1430 compatible = "rockchip,gpio-bank";
1434 gpio-controller;
1435 #gpio-cells = <2>;
1437 interrupt-controller;
1438 #interrupt-cells = <2>;
1441 pcfg_pull_up: pcfg-pull-up {
1442 bias-pull-up;
1445 pcfg_pull_down: pcfg-pull-down {
1446 bias-pull-down;
1449 pcfg_pull_none: pcfg-pull-none {
1450 bias-disable;
1453 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1454 bias-disable;
1455 drive-strength = <2>;
1458 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1459 bias-pull-up;
1460 drive-strength = <2>;
1463 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1464 bias-pull-up;
1465 drive-strength = <4>;
1468 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1469 bias-disable;
1470 drive-strength = <4>;
1473 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1474 bias-pull-down;
1475 drive-strength = <4>;
1478 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1479 bias-disable;
1480 drive-strength = <8>;
1483 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1484 bias-pull-up;
1485 drive-strength = <8>;
1488 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1489 bias-disable;
1490 drive-strength = <12>;
1493 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1494 bias-pull-up;
1495 drive-strength = <12>;
1498 pcfg_pull_none_smt: pcfg-pull-none-smt {
1499 bias-disable;
1500 input-schmitt-enable;
1503 pcfg_output_high: pcfg-output-high {
1504 output-high;
1507 pcfg_output_low: pcfg-output-low {
1508 output-low;
1511 pcfg_input_high: pcfg-input-high {
1512 bias-pull-up;
1513 input-enable;
1516 pcfg_input: pcfg-input {
1517 input-enable;
1521 i2c0_xfer: i2c0-xfer {
1529 i2c1_xfer: i2c1-xfer {
1537 i2c2_xfer: i2c2-xfer {
1545 i2c3_xfer: i2c3-xfer {
1553 tsadc_otp_pin: tsadc-otp-pin {
1558 tsadc_otp_out: tsadc-otp-out {
1565 uart0_xfer: uart0-xfer {
1571 uart0_cts: uart0-cts {
1576 uart0_rts: uart0-rts {
1583 uart1_xfer: uart1-xfer {
1589 uart1_cts: uart1-cts {
1594 uart1_rts: uart1-rts {
1600 uart2-m0 {
1601 uart2m0_xfer: uart2m0-xfer {
1608 uart2-m1 {
1609 uart2m1_xfer: uart2m1-xfer {
1616 uart3-m0 {
1617 uart3m0_xfer: uart3m0-xfer {
1623 uart3m0_cts: uart3m0-cts {
1628 uart3m0_rts: uart3m0-rts {
1634 uart3-m1 {
1635 uart3m1_xfer: uart3m1-xfer {
1641 uart3m1_cts: uart3m1-cts {
1646 uart3m1_rts: uart3m1-rts {
1653 uart4_xfer: uart4-xfer {
1659 uart4_cts: uart4-cts {
1664 uart4_rts: uart4-rts {
1671 uart5_xfer: uart5-xfer {
1677 uart5_cts: uart5-cts {
1682 uart5_rts: uart5-rts {
1689 spi0_clk: spi0-clk {
1694 spi0_csn: spi0-csn {
1699 spi0_miso: spi0-miso {
1704 spi0_mosi: spi0-mosi {
1709 spi0_clk_hs: spi0-clk-hs {
1714 spi0_miso_hs: spi0-miso-hs {
1719 spi0_mosi_hs: spi0-mosi-hs {
1726 spi1_clk: spi1-clk {
1731 spi1_csn0: spi1-csn0 {
1736 spi1_csn1: spi1-csn1 {
1741 spi1_miso: spi1-miso {
1746 spi1_mosi: spi1-mosi {
1751 spi1_clk_hs: spi1-clk-hs {
1756 spi1_miso_hs: spi1-miso-hs {
1761 spi1_mosi_hs: spi1-mosi-hs {
1768 pdm_clk0m0: pdm-clk0m0 {
1773 pdm_clk0m1: pdm-clk0m1 {
1778 pdm_clk1: pdm-clk1 {
1783 pdm_sdi0m0: pdm-sdi0m0 {
1788 pdm_sdi0m1: pdm-sdi0m1 {
1793 pdm_sdi1: pdm-sdi1 {
1798 pdm_sdi2: pdm-sdi2 {
1803 pdm_sdi3: pdm-sdi3 {
1808 pdm_clk0m0_sleep: pdm-clk0m0-sleep {
1813 pdm_clk0m_sleep1: pdm-clk0m1-sleep {
1818 pdm_clk1_sleep: pdm-clk1-sleep {
1823 pdm_sdi0m0_sleep: pdm-sdi0m0-sleep {
1828 pdm_sdi0m1_sleep: pdm-sdi0m1-sleep {
1833 pdm_sdi1_sleep: pdm-sdi1-sleep {
1838 pdm_sdi2_sleep: pdm-sdi2-sleep {
1843 pdm_sdi3_sleep: pdm-sdi3-sleep {
1850 i2s0_8ch_mclk: i2s0-8ch-mclk {
1855 i2s0_8ch_sclktx: i2s0-8ch-sclktx {
1860 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx {
1865 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx {
1870 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx {
1875 i2s0_8ch_sdo0: i2s0-8ch-sdo0 {
1880 i2s0_8ch_sdo1: i2s0-8ch-sdo1 {
1885 i2s0_8ch_sdo2: i2s0-8ch-sdo2 {
1890 i2s0_8ch_sdo3: i2s0-8ch-sdo3 {
1895 i2s0_8ch_sdi0: i2s0-8ch-sdi0 {
1900 i2s0_8ch_sdi1: i2s0-8ch-sdi1 {
1905 i2s0_8ch_sdi2: i2s0-8ch-sdi2 {
1910 i2s0_8ch_sdi3: i2s0-8ch-sdi3 {
1917 i2s1_2ch_mclk: i2s1-2ch-mclk {
1922 i2s1_2ch_sclk: i2s1-2ch-sclk {
1927 i2s1_2ch_lrck: i2s1-2ch-lrck {
1932 i2s1_2ch_sdi: i2s1-2ch-sdi {
1937 i2s1_2ch_sdo: i2s1-2ch-sdo {
1944 i2s2_2ch_mclk: i2s2-2ch-mclk {
1949 i2s2_2ch_sclk: i2s2-2ch-sclk {
1954 i2s2_2ch_lrck: i2s2-2ch-lrck {
1959 i2s2_2ch_sdi: i2s2-2ch-sdi {
1964 i2s2_2ch_sdo: i2s2-2ch-sdo {
1971 sdmmc_clk: sdmmc-clk {
1976 sdmmc_cmd: sdmmc-cmd {
1981 sdmmc_det: sdmmc-det {
1986 sdmmc_bus1: sdmmc-bus1 {
1991 sdmmc_bus4: sdmmc-bus4 {
2001 sdio_clk: sdio-clk {
2006 sdio_cmd: sdio-cmd {
2011 sdio_bus4: sdio-bus4 {
2021 emmc_clk: emmc-clk {
2026 emmc_cmd: emmc-cmd {
2031 emmc_rstnout: emmc-rstnout {
2036 emmc_bus1: emmc-bus1 {
2041 emmc_bus4: emmc-bus4 {
2049 emmc_bus8: emmc-bus8 {
2063 flash_cs0: flash-cs0 {
2068 flash_rdy: flash-rdy {
2073 flash_dqs: flash-dqs {
2078 flash_ale: flash-ale {
2083 flash_cle: flash-cle {
2088 flash_wrn: flash-wrn {
2093 flash_csl: flash-csl {
2098 flash_rdn: flash-rdn {
2103 flash_bus8: flash-bus8 {
2117 sfc_bus4: sfc-bus4 {
2125 sfc_bus2: sfc-bus2 {
2131 sfc_cs0: sfc-cs0 {
2136 sfc_clk: sfc-clk {
2143 lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin {
2148 lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin {
2153 lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin {
2158 lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin {
2163 lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins {
2191 lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins {
2213 lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins {
2233 lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins {
2254 lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins {
2269 lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins {
2284 pwm0_pin: pwm0-pin {
2291 pwm1_pin: pwm1-pin {
2298 pwm2_pin: pwm2-pin {
2305 pwm3_pin: pwm3-pin {
2312 pwm4_pin: pwm4-pin {
2319 pwm5_pin: pwm5-pin {
2326 pwm6_pin: pwm6-pin {
2333 pwm7_pin: pwm7-pin {
2340 rmii_pins: rmii-pins {
2353 mac_refclk_12ma: mac-refclk-12ma {
2358 mac_refclk: mac-refclk {
2364 cif-m0 {
2365 cif_clkout_m0: cif-clkout-m0 {
2370 dvp_d2d9_m0: dvp-d2d9-m0 {
2386 dvp_d0d1_m0: dvp-d0d1-m0 {
2392 dvp_d10d11_m0:d10-d11-m0 {
2399 cif-m1 {
2400 cif_clkout_m1: cif-clkout-m1 {
2405 dvp_d2d9_m1: dvp-d2d9-m1 {
2421 dvp_d0d1_m1: dvp-d0d1-m1 {
2427 dvp_d10d11_m1:d10-d11-m1 {
2435 isp_prelight: isp-prelight {