Lines Matching +full:0 +full:xec541000
20 #clock-cells = <0>;
21 clock-frequency = <0>;
27 #clock-cells = <0>;
28 clock-frequency = <0>;
31 cluster0_opp: opp-table-0 {
66 #size-cells = <0>;
88 a76_0: cpu@0 {
90 reg = <0>;
102 reg = <0x100>;
114 reg = <0x10000>;
126 reg = <0x10100>;
139 CPU_SLEEP_0: cpu-sleep-0 {
141 arm,psci-suspend-param = <0x0010000>;
149 L3_CA76_0: cache-controller-0 {
171 #clock-cells = <0>;
173 clock-frequency = <0>;
178 #clock-cells = <0>;
180 clock-frequency = <0>;
191 #clock-cells = <0>;
192 clock-frequency = <0>;
205 reg = <0 0xe6020000 0 0x0c>;
215 reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
216 <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>,
217 <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>,
218 <0 0xe6061000 0 0x16c>, <0 0xe6061800 0 0x16c>,
219 <0 0xe6068000 0 0x16c>;
225 reg = <0 0xe6050180 0 0x54>;
232 gpio-ranges = <&pfc 0 0 19>;
240 reg = <0 0xe6050980 0 0x54>;
247 gpio-ranges = <&pfc 0 32 29>;
255 reg = <0 0xe6058180 0 0x54>;
262 gpio-ranges = <&pfc 0 64 20>;
270 reg = <0 0xe6058980 0 0x54>;
277 gpio-ranges = <&pfc 0 96 30>;
285 reg = <0 0xe6060180 0 0x54>;
292 gpio-ranges = <&pfc 0 128 25>;
300 reg = <0 0xe6060980 0 0x54>;
307 gpio-ranges = <&pfc 0 160 21>;
315 reg = <0 0xe6061180 0 0x54>;
322 gpio-ranges = <&pfc 0 192 21>;
330 reg = <0 0xe6061980 0 0x54>;
337 gpio-ranges = <&pfc 0 224 21>;
345 reg = <0 0xe6068180 0 0x54>;
352 gpio-ranges = <&pfc 0 256 14>;
360 reg = <0 0xe60f0000 0 0x1004>;
373 reg = <0 0xe6130000 0 0x1004>;
392 reg = <0 0xe6140000 0 0x1004>;
411 reg = <0 0xe6148000 0 0x1004>;
429 reg = <0 0xe6150000 0 0x4000>;
433 #power-domain-cells = <0>;
439 reg = <0 0xe6160000 0 0x4000>;
444 reg = <0 0xe6180000 0 0x4000>;
450 reg = <0 0xe6198000 0 0x200>,
451 <0 0xe61a0000 0 0x200>,
452 <0 0xe61a8000 0 0x200>,
453 <0 0xe61b0000 0 0x200>;
464 reg = <0 0xe61c0000 0 0x200>;
465 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
478 reg = <0 0xe61e0000 0 0x30>;
491 reg = <0 0xe6fc0000 0 0x30>;
504 reg = <0 0xe6fd0000 0 0x30>;
517 reg = <0 0xe6fe0000 0 0x30>;
530 reg = <0 0xffc00000 0 0x30>;
544 reg = <0 0xe6500000 0 0x40>;
547 dmas = <&dmac0 0x91>, <&dmac0 0x90>,
548 <&dmac1 0x91>, <&dmac1 0x90>;
554 #size-cells = <0>;
561 reg = <0 0xe6508000 0 0x40>;
564 dmas = <&dmac0 0x93>, <&dmac0 0x92>,
565 <&dmac1 0x93>, <&dmac1 0x92>;
571 #size-cells = <0>;
578 reg = <0 0xe6510000 0 0x40>;
581 dmas = <&dmac0 0x95>, <&dmac0 0x94>,
582 <&dmac1 0x95>, <&dmac1 0x94>;
588 #size-cells = <0>;
595 reg = <0 0xe66d0000 0 0x40>;
598 dmas = <&dmac0 0x97>, <&dmac0 0x96>,
599 <&dmac1 0x97>, <&dmac1 0x96>;
605 #size-cells = <0>;
612 reg = <0 0xe66d8000 0 0x40>;
616 dmas = <&dmac0 0x99>, <&dmac0 0x98>,
617 <&dmac1 0x99>, <&dmac1 0x98>;
622 #size-cells = <0>;
629 reg = <0 0xe66e0000 0 0x40>;
632 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>,
633 <&dmac1 0x9b>, <&dmac1 0x9a>;
639 #size-cells = <0>;
646 reg = <0 0xe6540000 0 0x60>;
652 dmas = <&dmac0 0x31>, <&dmac0 0x30>,
653 <&dmac1 0x31>, <&dmac1 0x30>;
663 reg = <0 0xe6550000 0 0x60>;
669 dmas = <&dmac0 0x33>, <&dmac0 0x32>,
670 <&dmac1 0x33>, <&dmac1 0x32>;
680 reg = <0 0xe6560000 0 0x60>;
686 dmas = <&dmac0 0x35>, <&dmac0 0x34>,
687 <&dmac1 0x35>, <&dmac1 0x34>;
697 reg = <0 0xe66a0000 0 0x60>;
703 dmas = <&dmac0 0x37>, <&dmac0 0x36>,
704 <&dmac1 0x37>, <&dmac1 0x36>;
714 reg = <0 0xe6660000 0 0x8500>;
764 reg = <0 0xe6800000 0 0x800>;
801 rx-internal-delay-ps = <0>;
802 tx-internal-delay-ps = <0>;
804 #size-cells = <0>;
811 reg = <0 0xe6810000 0 0x800>;
848 rx-internal-delay-ps = <0>;
849 tx-internal-delay-ps = <0>;
851 #size-cells = <0>;
858 reg = <0 0xe6820000 0 0x1000>;
895 rx-internal-delay-ps = <0>;
896 tx-internal-delay-ps = <0>;
898 #size-cells = <0>;
904 reg = <0 0xe6e30000 0 0x10>;
914 reg = <0 0xe6e31000 0 0x10>;
924 reg = <0 0xe6e32000 0 0x10>;
934 reg = <0 0xe6e33000 0 0x10>;
944 reg = <0 0xe6e34000 0 0x10>;
954 reg = <0 0xe6e35000 0 0x10>;
964 reg = <0 0xe6e36000 0 0x10>;
974 reg = <0 0xe6e37000 0 0x10>;
984 reg = <0 0xe6e38000 0 0x10>;
994 reg = <0 0xe6e39000 0 0x10>;
1005 reg = <0 0xe6e60000 0 64>;
1011 dmas = <&dmac0 0x51>, <&dmac0 0x50>,
1012 <&dmac1 0x51>, <&dmac1 0x50>;
1022 reg = <0 0xe6e68000 0 64>;
1028 dmas = <&dmac0 0x53>, <&dmac0 0x52>,
1029 <&dmac1 0x53>, <&dmac1 0x52>;
1039 reg = <0 0xe6c50000 0 64>;
1045 dmas = <&dmac0 0x57>, <&dmac0 0x56>,
1046 <&dmac1 0x57>, <&dmac1 0x56>;
1056 reg = <0 0xe6c40000 0 64>;
1062 dmas = <&dmac0 0x59>, <&dmac0 0x58>,
1063 <&dmac1 0x59>, <&dmac1 0x58>;
1072 reg = <0 0xe6e80000 0 0x148>;
1084 reg = <0 0xe6e90000 0 0x0064>;
1087 dmas = <&dmac0 0x41>, <&dmac0 0x40>,
1088 <&dmac1 0x41>, <&dmac1 0x40>;
1093 #size-cells = <0>;
1100 reg = <0 0xe6ea0000 0 0x0064>;
1103 dmas = <&dmac0 0x43>, <&dmac0 0x42>,
1104 <&dmac1 0x43>, <&dmac1 0x42>;
1109 #size-cells = <0>;
1116 reg = <0 0xe6c00000 0 0x0064>;
1119 dmas = <&dmac0 0x45>, <&dmac0 0x44>,
1120 <&dmac1 0x45>, <&dmac1 0x44>;
1125 #size-cells = <0>;
1132 reg = <0 0xe6c10000 0 0x0064>;
1135 dmas = <&dmac0 0x47>, <&dmac0 0x46>,
1136 <&dmac1 0x47>, <&dmac1 0x46>;
1141 #size-cells = <0>;
1148 reg = <0 0xe6c20000 0 0x0064>;
1151 dmas = <&dmac0 0x49>, <&dmac0 0x48>,
1152 <&dmac1 0x49>, <&dmac1 0x48>;
1157 #size-cells = <0>;
1164 reg = <0 0xe6c28000 0 0x0064>;
1167 dmas = <&dmac0 0x4b>, <&dmac0 0x4a>,
1168 <&dmac1 0x4b>, <&dmac1 0x4a>;
1173 #size-cells = <0>;
1179 reg = <0 0xe6ef0000 0 0x1000>;
1184 renesas,id = <0>;
1189 #size-cells = <0>;
1193 #size-cells = <0>;
1197 vin00isp0: endpoint@0 {
1198 reg = <0>;
1207 reg = <0 0xe6ef1000 0 0x1000>;
1217 #size-cells = <0>;
1221 #size-cells = <0>;
1225 vin01isp0: endpoint@0 {
1226 reg = <0>;
1235 reg = <0 0xe6ef2000 0 0x1000>;
1245 #size-cells = <0>;
1249 #size-cells = <0>;
1253 vin02isp0: endpoint@0 {
1254 reg = <0>;
1263 reg = <0 0xe6ef3000 0 0x1000>;
1273 #size-cells = <0>;
1277 #size-cells = <0>;
1281 vin03isp0: endpoint@0 {
1282 reg = <0>;
1291 reg = <0 0xe6ef4000 0 0x1000>;
1301 #size-cells = <0>;
1305 #size-cells = <0>;
1309 vin04isp0: endpoint@0 {
1310 reg = <0>;
1319 reg = <0 0xe6ef5000 0 0x1000>;
1329 #size-cells = <0>;
1333 #size-cells = <0>;
1337 vin05isp0: endpoint@0 {
1338 reg = <0>;
1347 reg = <0 0xe6ef6000 0 0x1000>;
1357 #size-cells = <0>;
1361 #size-cells = <0>;
1365 vin06isp0: endpoint@0 {
1366 reg = <0>;
1375 reg = <0 0xe6ef7000 0 0x1000>;
1385 #size-cells = <0>;
1389 #size-cells = <0>;
1393 vin07isp0: endpoint@0 {
1394 reg = <0>;
1403 reg = <0 0xe6ef8000 0 0x1000>;
1413 #size-cells = <0>;
1417 #size-cells = <0>;
1431 reg = <0 0xe6ef9000 0 0x1000>;
1441 #size-cells = <0>;
1445 #size-cells = <0>;
1459 reg = <0 0xe6efa000 0 0x1000>;
1469 #size-cells = <0>;
1473 #size-cells = <0>;
1487 reg = <0 0xe6efb000 0 0x1000>;
1497 #size-cells = <0>;
1501 #size-cells = <0>;
1515 reg = <0 0xe6efc000 0 0x1000>;
1525 #size-cells = <0>;
1529 #size-cells = <0>;
1543 reg = <0 0xe6efd000 0 0x1000>;
1553 #size-cells = <0>;
1557 #size-cells = <0>;
1571 reg = <0 0xe6efe000 0 0x1000>;
1581 #size-cells = <0>;
1585 #size-cells = <0>;
1599 reg = <0 0xe6eff000 0 0x1000>;
1609 #size-cells = <0>;
1613 #size-cells = <0>;
1628 reg = <0 0xe7350000 0 0x1000>,
1629 <0 0xe7300000 0 0x10000>;
1658 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
1671 reg = <0 0xe7351000 0 0x1000>,
1672 <0 0xe7310000 0 0x10000>;
1715 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1721 * clkout : #clock-cells = <0>; <&rcar_sound>;
1725 reg = <0 0xec5a0000 0 0x020>,
1726 <0 0xec540000 0 0x1000>,
1727 <0 0xec541000 0 0x050>,
1728 <0 0xec400000 0 0x40000>;
1732 clock-names = "ssiu.0", "ssi.0", "clkin";
1735 reset-names = "ssiu.0", "ssi.0";
1739 ssiu00: ssiu-0 {
1740 dmas = <&dmac0 0x6e>, <&dmac0 0x6f>;
1744 dmas = <&dmac0 0x6c>, <&dmac0 0x6d>;
1748 dmas = <&dmac0 0x6a>, <&dmac0 0x6b>;
1752 dmas = <&dmac0 0x68>, <&dmac0 0x69>;
1756 dmas = <&dmac0 0x66>, <&dmac0 0x67>;
1760 dmas = <&dmac0 0x64>, <&dmac0 0x65>;
1764 dmas = <&dmac0 0x62>, <&dmac0 0x63>;
1768 dmas = <&dmac0 0x60>, <&dmac0 0x61>;
1774 ssi0: ssi-0 {
1783 reg = <0 0xee480000 0 0x20000>;
1792 reg = <0 0xee4c0000 0 0x20000>;
1801 reg = <0 0xeed00000 0 0x20000>;
1810 reg = <0 0xeed40000 0 0x20000>;
1819 reg = <0 0xeed80000 0 0x20000>;
1828 reg = <0 0xeedc0000 0 0x20000>;
1837 reg = <0 0xeee00000 0 0x20000>;
1846 reg = <0 0xeee80000 0 0x20000>;
1855 reg = <0 0xeeec0000 0 0x20000>;
1864 reg = <0 0xeef00000 0 0x20000>;
1873 reg = <0 0xeef40000 0 0x20000>;
1882 reg = <0 0xeefc0000 0 0x20000>;
1892 reg = <0 0xee140000 0 0x2000>;
1907 reg = <0 0xee200000 0 0x200>,
1908 <0 0x08000000 0 0x04000000>,
1909 <0 0xee208000 0 0x100>;
1916 #size-cells = <0>;
1923 #address-cells = <0>;
1925 reg = <0x0 0xf1000000 0 0x20000>,
1926 <0x0 0xf1060000 0 0x110000>;
1932 reg = <0 0xfe500000 0 0x40000>;
1941 #size-cells = <0>;
1943 port@0 {
1944 reg = <0>;
1958 reg = <0 0xfe540000 0 0x40000>;
1967 #size-cells = <0>;
1969 port@0 {
1970 reg = <0>;
1984 reg = <0 0xfea10000 0 0x200>;
1992 reg = <0 0xfea11000 0 0x200>;
2000 reg = <0 0xfea20000 0 0x7000>;
2011 reg = <0 0xfea28000 0 0x7000>;
2022 reg = <0 0xfeb00000 0 0x40000>;
2026 clock-names = "du.0";
2029 reset-names = "du.0";
2030 renesas,vsps = <&vspd0 0>, <&vspd1 0>;
2036 #size-cells = <0>;
2038 port@0 {
2039 reg = <0>;
2056 reg = <0 0xfed00000 0 0x10000>;
2065 #size-cells = <0>;
2067 port@0 {
2069 #size-cells = <0>;
2071 reg = <0>;
2073 isp0csi40: endpoint@0 {
2074 reg = <0>;
2139 reg = <0 0xfed20000 0 0x10000>;
2148 #size-cells = <0>;
2150 port@0 {
2152 #size-cells = <0>;
2154 reg = <0>;
2222 reg = <0 0xfed80000 0 0x10000>;
2234 #size-cells = <0>;
2236 port@0 {
2237 reg = <0>;
2251 reg = <0 0xfed90000 0 0x10000>;
2263 #size-cells = <0>;
2265 port@0 {
2266 reg = <0>;
2280 reg = <0 0xfff00044 0 4>;
2288 thermal-sensors = <&tsc 0>;