Lines Matching +full:0 +full:xe6130000
22 #clock-cells = <0>;
23 clock-frequency = <0>;
28 #size-cells = <0>;
30 a53_0: cpu@0 {
33 reg = <0>;
80 #clock-cells = <0>;
82 clock-frequency = <0>;
87 #clock-cells = <0>;
89 clock-frequency = <0>;
95 #clock-cells = <0>;
96 clock-frequency = <0>;
116 #clock-cells = <0>;
117 clock-frequency = <0>;
131 reg = <0 0xe6020000 0 0x0c>;
142 reg = <0 0xe6050000 0 0x50>;
146 gpio-ranges = <&pfc 0 0 22>;
157 reg = <0 0xe6051000 0 0x50>;
161 gpio-ranges = <&pfc 0 32 28>;
172 reg = <0 0xe6052000 0 0x50>;
176 gpio-ranges = <&pfc 0 64 30>;
187 reg = <0 0xe6053000 0 0x50>;
191 gpio-ranges = <&pfc 0 96 17>;
202 reg = <0 0xe6054000 0 0x50>;
206 gpio-ranges = <&pfc 0 128 25>;
217 reg = <0 0xe6055000 0 0x50>;
221 gpio-ranges = <&pfc 0 160 15>;
231 reg = <0 0xe6060000 0 0x50c>;
237 reg = <0 0xe60f0000 0 0x1004>;
250 reg = <0 0xe6130000 0 0x1004>;
269 reg = <0 0xe6140000 0 0x1004>;
288 reg = <0 0xe6148000 0 0x1004>;
306 reg = <0 0xe6150000 0 0x1000>;
310 #power-domain-cells = <0>;
316 reg = <0 0xe6160000 0 0x200>;
321 reg = <0 0xe6180000 0 0x440>;
327 reg = <0 0xe6198000 0 0x100>,
328 <0 0xe61a0000 0 0x100>;
342 reg = <0 0xe61c0000 0 0x200>;
343 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
356 reg = <0 0xe61e0000 0 0x30>;
369 reg = <0 0xe6fc0000 0 0x30>;
382 reg = <0 0xe6fd0000 0 0x30>;
395 reg = <0 0xe6fe0000 0 0x30>;
408 reg = <0 0xffc00000 0 0x30>;
422 reg = <0 0xe6500000 0 0x40>;
427 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
428 <&dmac2 0x91>, <&dmac2 0x90>;
432 #size-cells = <0>;
439 reg = <0 0xe6508000 0 0x40>;
444 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
445 <&dmac2 0x93>, <&dmac2 0x92>;
449 #size-cells = <0>;
456 reg = <0 0xe6510000 0 0x40>;
461 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
462 <&dmac2 0x95>, <&dmac2 0x94>;
466 #size-cells = <0>;
473 reg = <0 0xe66d0000 0 0x40>;
480 #size-cells = <0>;
487 reg = <0 0xe66d8000 0 0x40>;
494 #size-cells = <0>;
501 reg = <0 0xe66e0000 0 0x40>;
506 dmas = <&dmac1 0x9b>, <&dmac1 0x9a>,
507 <&dmac2 0x9b>, <&dmac2 0x9a>;
511 #size-cells = <0>;
519 reg = <0 0xe6540000 0 0x60>;
525 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
526 <&dmac2 0x31>, <&dmac2 0x30>;
537 reg = <0 0xe6550000 0 0x60>;
543 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
544 <&dmac2 0x33>, <&dmac2 0x32>;
555 reg = <0 0xe6560000 0 0x60>;
561 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
562 <&dmac2 0x35>, <&dmac2 0x34>;
573 reg = <0 0xe66a0000 0 0x60>;
579 dmas = <&dmac1 0x37>, <&dmac1 0x36>,
580 <&dmac2 0x37>, <&dmac2 0x36>;
589 reg = <0 0xe65d0000 0 0x8000>;
590 #phy-cells = <0>;
600 reg = <0 0xe66c0000 0 0x8000>;
626 reg = <0 0xe6800000 0 0x800>;
664 rx-internal-delay-ps = <0>;
668 #size-cells = <0>;
674 reg = <0 0xe6e30000 0 0x10>;
684 reg = <0 0xe6e31000 0 0x10>;
694 reg = <0 0xe6e32000 0 0x10>;
704 reg = <0 0xe6e33000 0 0x10>;
714 reg = <0 0xe6e34000 0 0x10>;
726 reg = <0 0xe6e60000 0 0x40>;
732 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
733 <&dmac2 0x51>, <&dmac2 0x50>;
744 reg = <0 0xe6e68000 0 0x40>;
750 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
751 <&dmac2 0x53>, <&dmac2 0x52>;
762 reg = <0 0xe6c50000 0 0x40>;
768 dmas = <&dmac1 0x57>, <&dmac1 0x56>,
769 <&dmac2 0x57>, <&dmac2 0x56>;
780 reg = <0 0xe6c40000 0 0x40>;
786 dmas = <&dmac1 0x59>, <&dmac1 0x58>,
787 <&dmac2 0x59>, <&dmac2 0x58>;
796 reg = <0 0xe6e80000 0 0x148>;
808 reg = <0 0xe6e90000 0 0x64>;
814 #size-cells = <0>;
821 reg = <0 0xe6ea0000 0 0x0064>;
827 #size-cells = <0>;
834 reg = <0 0xe6c00000 0 0x0064>;
840 #size-cells = <0>;
847 reg = <0 0xe6c10000 0 0x0064>;
853 #size-cells = <0>;
859 reg = <0 0xe6ef0000 0 0x1000>;
864 renesas,id = <0>;
869 #size-cells = <0>;
873 #size-cells = <0>;
887 reg = <0 0xe6ef1000 0 0x1000>;
897 #size-cells = <0>;
901 #size-cells = <0>;
915 reg = <0 0xe6ef2000 0 0x1000>;
925 #size-cells = <0>;
929 #size-cells = <0>;
943 reg = <0 0xe6ef3000 0 0x1000>;
953 #size-cells = <0>;
957 #size-cells = <0>;
971 reg = <0 0xe6ef4000 0 0x1000>;
981 #size-cells = <0>;
985 #size-cells = <0>;
999 reg = <0 0xe6ef5000 0 0x1000>;
1009 #size-cells = <0>;
1013 #size-cells = <0>;
1027 reg = <0 0xe6ef6000 0 0x1000>;
1037 #size-cells = <0>;
1041 #size-cells = <0>;
1055 reg = <0 0xe6ef7000 0 0x1000>;
1065 #size-cells = <0>;
1069 #size-cells = <0>;
1083 reg = <0 0xe6ef8000 0 0x1000>;
1094 reg = <0 0xe6ef9000 0 0x1000>;
1105 reg = <0 0xe6efa000 0 0x1000>;
1116 reg = <0 0xe6efb000 0 0x1000>;
1127 reg = <0 0xe6efc000 0 0x1000>;
1138 reg = <0 0xe6efd000 0 0x1000>;
1149 reg = <0 0xe6efe000 0 0x1000>;
1160 reg = <0 0xe6eff000 0 0x1000>;
1172 reg = <0 0xe7300000 0 0x10000>;
1201 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
1214 reg = <0 0xe7310000 0 0x10000>;
1255 reg = <0 0xe7400000 0 0x1000>;
1261 #size-cells = <0>;
1267 reg = <0 0xe7740000 0 0x1000>;
1268 renesas,ipmmu-main = <&ipmmu_mm 0>;
1275 reg = <0 0xff8b0000 0 0x1000>;
1283 reg = <0 0xe67b0000 0 0x1000>;
1292 reg = <0 0xffc80000 0 0x1000>;
1300 reg = <0 0xfe990000 0 0x1000>;
1308 reg = <0 0xfebd0000 0 0x1000>;
1316 reg = <0 0xe7b00000 0 0x1000>;
1324 reg = <0 0xe7960000 0 0x1000>;
1333 reg = <0 0xee140000 0 0x2000>;
1347 reg = <0 0xee200000 0 0x200>,
1348 <0 0x08000000 0 0x4000000>,
1349 <0 0xee208000 0 0x100>;
1356 #size-cells = <0>;
1363 #address-cells = <0>;
1365 reg = <0x0 0xf1010000 0 0x1000>,
1366 <0x0 0xf1020000 0 0x20000>,
1367 <0x0 0xf1040000 0 0x20000>,
1368 <0x0 0xf1060000 0 0x20000>;
1380 reg = <0 0xfe000000 0 0x80000>;
1383 bus-range = <0x00 0xff>;
1385 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x0100000>,
1386 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x0200000>,
1387 <0x02000000 0 0x30000000 0 0x30000000 0 0x8000000>,
1388 <0x42000000 0 0x38000000 0 0x38000000 0 0x8000000>;
1390 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
1395 interrupt-map-mask = <0 0 0 0>;
1396 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1403 iommu-map = <0 &ipmmu_vi0 5 1>;
1404 iommu-map-mask = <0>;
1410 reg = <0 0xfea20000 0 0x5000>;
1420 reg = <0 0xfea27000 0 0x200>;
1428 reg = <0 0xfeaa0000 0 0x10000>;
1437 #size-cells = <0>;
1439 port@0 {
1440 reg = <0>;
1445 #size-cells = <0>;
1449 csi40vin0: endpoint@0 {
1450 reg = <0>;
1471 reg = <0 0xfeab0000 0 0x10000>;
1480 #size-cells = <0>;
1482 port@0 {
1483 reg = <0>;
1488 #size-cells = <0>;
1492 csi41vin4: endpoint@0 {
1493 reg = <0>;
1514 reg = <0 0xfeb00000 0 0x80000>;
1517 clock-names = "du.0";
1520 reset-names = "du.0";
1521 renesas,vsps = <&vspd0 0>;
1527 #size-cells = <0>;
1529 port@0 {
1530 reg = <0>;
1544 reg = <0 0xfeb90000 0 0x14>;
1552 #size-cells = <0>;
1554 port@0 {
1555 reg = <0>;
1570 reg = <0 0xfff00044 0 4>;
1578 thermal-sensors = <&tsc 0>;