Lines Matching +full:0 +full:xec5a0000
23 * The external audio clocks are configured as 0 Hz fixed frequency
29 #clock-cells = <0>;
30 clock-frequency = <0>;
35 #clock-cells = <0>;
36 clock-frequency = <0>;
41 #clock-cells = <0>;
42 clock-frequency = <0>;
48 #clock-cells = <0>;
49 clock-frequency = <0>;
52 cluster0_opp: opp-table-0 {
92 #size-cells = <0>;
94 a57_0: cpu@0 {
96 reg = <0x0>;
110 reg = <0x1>;
120 L2_CA57: cache-controller-0 {
130 CPU_SLEEP_0: cpu-sleep-0 {
132 arm,psci-suspend-param = <0x0010000>;
143 #clock-cells = <0>;
145 clock-frequency = <0>;
150 #clock-cells = <0>;
152 clock-frequency = <0>;
158 #clock-cells = <0>;
159 clock-frequency = <0>;
178 #clock-cells = <0>;
179 clock-frequency = <0>;
192 reg = <0 0xe6020000 0 0x0c>;
203 reg = <0 0xe6050000 0 0x50>;
207 gpio-ranges = <&pfc 0 0 16>;
218 reg = <0 0xe6051000 0 0x50>;
222 gpio-ranges = <&pfc 0 32 29>;
233 reg = <0 0xe6052000 0 0x50>;
237 gpio-ranges = <&pfc 0 64 15>;
248 reg = <0 0xe6053000 0 0x50>;
252 gpio-ranges = <&pfc 0 96 16>;
263 reg = <0 0xe6054000 0 0x50>;
267 gpio-ranges = <&pfc 0 128 18>;
278 reg = <0 0xe6055000 0 0x50>;
282 gpio-ranges = <&pfc 0 160 26>;
293 reg = <0 0xe6055400 0 0x50>;
297 gpio-ranges = <&pfc 0 192 32>;
308 reg = <0 0xe6055800 0 0x50>;
312 gpio-ranges = <&pfc 0 224 4>;
322 reg = <0 0xe6060000 0 0x50c>;
328 reg = <0 0xe60f0000 0 0x1004>;
341 reg = <0 0xe6130000 0 0x1004>;
360 reg = <0 0xe6140000 0 0x1004>;
379 reg = <0 0xe6148000 0 0x1004>;
397 reg = <0 0xe6150000 0 0x1000>;
401 #power-domain-cells = <0>;
407 reg = <0 0xe6160000 0 0x0200>;
412 reg = <0 0xe6180000 0 0x0400>;
418 reg = <0 0xe6198000 0 0x100>,
419 <0 0xe61a0000 0 0x100>,
420 <0 0xe61a8000 0 0x100>;
434 reg = <0 0xe61c0000 0 0x200>;
435 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
448 reg = <0 0xe61e0000 0 0x30>;
461 reg = <0 0xe6fc0000 0 0x30>;
474 reg = <0 0xe6fd0000 0 0x30>;
487 reg = <0 0xe6fe0000 0 0x30>;
500 reg = <0 0xffc00000 0 0x30>;
513 #size-cells = <0>;
516 reg = <0 0xe6500000 0 0x40>;
521 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
522 <&dmac2 0x91>, <&dmac2 0x90>;
530 #size-cells = <0>;
533 reg = <0 0xe6508000 0 0x40>;
538 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
539 <&dmac2 0x93>, <&dmac2 0x92>;
547 #size-cells = <0>;
550 reg = <0 0xe6510000 0 0x40>;
555 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
556 <&dmac2 0x95>, <&dmac2 0x94>;
564 #size-cells = <0>;
567 reg = <0 0xe66d0000 0 0x40>;
572 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
580 #size-cells = <0>;
583 reg = <0 0xe66d8000 0 0x40>;
588 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
596 #size-cells = <0>;
599 reg = <0 0xe66e0000 0 0x40>;
604 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
612 #size-cells = <0>;
615 reg = <0 0xe66e8000 0 0x40>;
620 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
628 #size-cells = <0>;
632 reg = <0 0xe60b0000 0 0x425>;
637 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
646 reg = <0 0xe6540000 0 0x60>;
652 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
653 <&dmac2 0x31>, <&dmac2 0x30>;
664 reg = <0 0xe6550000 0 0x60>;
670 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
671 <&dmac2 0x33>, <&dmac2 0x32>;
682 reg = <0 0xe6560000 0 0x60>;
688 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
689 <&dmac2 0x35>, <&dmac2 0x34>;
700 reg = <0 0xe66a0000 0 0x60>;
706 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
717 reg = <0 0xe66b0000 0 0x60>;
723 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
733 reg = <0 0xe6590000 0 0x200>;
736 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
737 <&usb_dmac1 0>, <&usb_dmac1 1>;
750 reg = <0 0xe65a0000 0 0x100>;
764 reg = <0 0xe65b0000 0 0x100>;
778 reg = <0 0xe65ee000 0 0x90>;
784 #phy-cells = <0>;
791 reg = <0x0 0xe6601000 0 0x1000>;
800 reg = <0 0xe6700000 0 0x10000>;
829 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
842 reg = <0 0xe7300000 0 0x10000>;
871 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
884 reg = <0 0xe7310000 0 0x10000>;
925 reg = <0 0xe6740000 0 0x1000>;
926 renesas,ipmmu-main = <&ipmmu_mm 0>;
933 reg = <0 0xe7740000 0 0x1000>;
941 reg = <0 0xe6570000 0 0x1000>;
949 reg = <0 0xe67b0000 0 0x1000>;
958 reg = <0 0xec670000 0 0x1000>;
966 reg = <0 0xfd800000 0 0x1000>;
974 reg = <0 0xffc80000 0 0x1000>;
982 reg = <0 0xfe6b0000 0 0x1000>;
990 reg = <0 0xfebd0000 0 0x1000>;
998 reg = <0 0xfe990000 0 0x1000>;
1007 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
1045 rx-internal-delay-ps = <0>;
1046 tx-internal-delay-ps = <0>;
1049 #size-cells = <0>;
1056 reg = <0 0xe6c30000 0 0x1000>;
1072 reg = <0 0xe6c38000 0 0x1000>;
1088 reg = <0 0xe66c0000 0 0x8000>;
1113 reg = <0 0xe6e30000 0 8>;
1123 reg = <0 0xe6e31000 0 8>;
1133 reg = <0 0xe6e32000 0 8>;
1143 reg = <0 0xe6e33000 0 8>;
1153 reg = <0 0xe6e34000 0 8>;
1163 reg = <0 0xe6e35000 0 8>;
1173 reg = <0 0xe6e36000 0 8>;
1184 reg = <0 0xe6e60000 0 64>;
1190 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1191 <&dmac2 0x51>, <&dmac2 0x50>;
1201 reg = <0 0xe6e68000 0 64>;
1207 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1208 <&dmac2 0x53>, <&dmac2 0x52>;
1218 reg = <0 0xe6e88000 0 64>;
1224 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1225 <&dmac2 0x13>, <&dmac2 0x12>;
1235 reg = <0 0xe6c50000 0 64>;
1241 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1251 reg = <0 0xe6c40000 0 64>;
1257 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1267 reg = <0 0xe6f30000 0 64>;
1273 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1274 <&dmac2 0x5b>, <&dmac2 0x5a>;
1283 reg = <0 0xe6e80000 0 0x148>;
1295 reg = <0 0xe6e90000 0 0x0064>;
1298 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1299 <&dmac2 0x41>, <&dmac2 0x40>;
1304 #size-cells = <0>;
1311 reg = <0 0xe6ea0000 0 0x0064>;
1314 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1315 <&dmac2 0x43>, <&dmac2 0x42>;
1320 #size-cells = <0>;
1327 reg = <0 0xe6c00000 0 0x0064>;
1330 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1335 #size-cells = <0>;
1342 reg = <0 0xe6c10000 0 0x0064>;
1345 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1350 #size-cells = <0>;
1356 reg = <0 0xe6ef0000 0 0x1000>;
1361 renesas,id = <0>;
1366 #size-cells = <0>;
1370 #size-cells = <0>;
1374 vin0csi20: endpoint@0 {
1375 reg = <0>;
1388 reg = <0 0xe6ef1000 0 0x1000>;
1398 #size-cells = <0>;
1402 #size-cells = <0>;
1406 vin1csi20: endpoint@0 {
1407 reg = <0>;
1420 reg = <0 0xe6ef2000 0 0x1000>;
1430 #size-cells = <0>;
1434 #size-cells = <0>;
1438 vin2csi20: endpoint@0 {
1439 reg = <0>;
1452 reg = <0 0xe6ef3000 0 0x1000>;
1462 #size-cells = <0>;
1466 #size-cells = <0>;
1470 vin3csi20: endpoint@0 {
1471 reg = <0>;
1484 reg = <0 0xe6ef4000 0 0x1000>;
1494 #size-cells = <0>;
1498 #size-cells = <0>;
1502 vin4csi20: endpoint@0 {
1503 reg = <0>;
1516 reg = <0 0xe6ef5000 0 0x1000>;
1526 #size-cells = <0>;
1530 #size-cells = <0>;
1534 vin5csi20: endpoint@0 {
1535 reg = <0>;
1548 reg = <0 0xe6ef6000 0 0x1000>;
1558 #size-cells = <0>;
1562 #size-cells = <0>;
1566 vin6csi20: endpoint@0 {
1567 reg = <0>;
1580 reg = <0 0xe6ef7000 0 0x1000>;
1590 #size-cells = <0>;
1594 #size-cells = <0>;
1598 vin7csi20: endpoint@0 {
1599 reg = <0>;
1613 reg = <0 0xe6f40000 0 0x84>;
1617 dmas = <&dmac1 0x20>, <&dmac2 0x20>;
1628 reg = <0 0xe6f50000 0 0x84>;
1632 dmas = <&dmac1 0x22>, <&dmac2 0x22>;
1643 reg = <0 0xe6f60000 0 0x84>;
1647 dmas = <&dmac1 0x24>, <&dmac2 0x24>;
1658 reg = <0 0xe6f70000 0 0x84>;
1662 dmas = <&dmac1 0x26>, <&dmac2 0x26>;
1673 reg = <0 0xe6f80000 0 0x84>;
1677 dmas = <&dmac1 0x28>, <&dmac2 0x28>;
1688 reg = <0 0xe6f90000 0 0x84>;
1692 dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
1703 reg = <0 0xe6fa0000 0 0x84>;
1707 dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
1718 reg = <0 0xe6fb0000 0 0x84>;
1722 dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
1734 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1740 * clkout : #clock-cells = <0>; <&rcar_sound>;
1744 reg = <0 0xec500000 0 0x1000>, /* SCU */
1745 <0 0xec5a0000 0 0x100>, /* ADG */
1746 <0 0xec540000 0 0x1000>, /* SSIU */
1747 <0 0xec541000 0 0x280>, /* SSI */
1748 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1771 "ssi.1", "ssi.0",
1774 "src.1", "src.0",
1775 "mix.1", "mix.0",
1776 "ctu.1", "ctu.0",
1777 "dvc.0", "dvc.1",
1789 "ssi.1", "ssi.0";
1793 dvc0: dvc-0 {
1794 dmas = <&audma1 0xbc>;
1798 dmas = <&audma1 0xbe>;
1804 mix0: mix-0 { };
1809 ctu00: ctu-0 { };
1820 src0: src-0 {
1822 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1827 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1832 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1837 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1842 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1847 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1852 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1857 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1862 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1867 dmas = <&audma0 0x97>, <&audma1 0xba>;
1873 ssiu00: ssiu-0 {
1874 dmas = <&audma0 0x15>, <&audma1 0x16>;
1878 dmas = <&audma0 0x35>, <&audma1 0x36>;
1882 dmas = <&audma0 0x37>, <&audma1 0x38>;
1886 dmas = <&audma0 0x47>, <&audma1 0x48>;
1890 dmas = <&audma0 0x3F>, <&audma1 0x40>;
1894 dmas = <&audma0 0x43>, <&audma1 0x44>;
1898 dmas = <&audma0 0x4F>, <&audma1 0x50>;
1902 dmas = <&audma0 0x53>, <&audma1 0x54>;
1906 dmas = <&audma0 0x49>, <&audma1 0x4a>;
1910 dmas = <&audma0 0x4B>, <&audma1 0x4C>;
1914 dmas = <&audma0 0x57>, <&audma1 0x58>;
1918 dmas = <&audma0 0x59>, <&audma1 0x5A>;
1922 dmas = <&audma0 0x5F>, <&audma1 0x60>;
1926 dmas = <&audma0 0xC3>, <&audma1 0xC4>;
1930 dmas = <&audma0 0xC7>, <&audma1 0xC8>;
1934 dmas = <&audma0 0xCB>, <&audma1 0xCC>;
1938 dmas = <&audma0 0x63>, <&audma1 0x64>;
1942 dmas = <&audma0 0x67>, <&audma1 0x68>;
1946 dmas = <&audma0 0x6B>, <&audma1 0x6C>;
1950 dmas = <&audma0 0x6D>, <&audma1 0x6E>;
1954 dmas = <&audma0 0xCF>, <&audma1 0xCE>;
1958 dmas = <&audma0 0xEB>, <&audma1 0xEC>;
1962 dmas = <&audma0 0xED>, <&audma1 0xEE>;
1966 dmas = <&audma0 0xEF>, <&audma1 0xF0>;
1970 dmas = <&audma0 0x6f>, <&audma1 0x70>;
1974 dmas = <&audma0 0x21>, <&audma1 0x22>;
1978 dmas = <&audma0 0x23>, <&audma1 0x24>;
1982 dmas = <&audma0 0x25>, <&audma1 0x26>;
1986 dmas = <&audma0 0x27>, <&audma1 0x28>;
1990 dmas = <&audma0 0x29>, <&audma1 0x2A>;
1994 dmas = <&audma0 0x2B>, <&audma1 0x2C>;
1998 dmas = <&audma0 0x2D>, <&audma1 0x2E>;
2002 dmas = <&audma0 0x71>, <&audma1 0x72>;
2006 dmas = <&audma0 0x17>, <&audma1 0x18>;
2010 dmas = <&audma0 0x19>, <&audma1 0x1A>;
2014 dmas = <&audma0 0x1B>, <&audma1 0x1C>;
2018 dmas = <&audma0 0x1D>, <&audma1 0x1E>;
2022 dmas = <&audma0 0x1F>, <&audma1 0x20>;
2026 dmas = <&audma0 0x31>, <&audma1 0x32>;
2030 dmas = <&audma0 0x33>, <&audma1 0x34>;
2034 dmas = <&audma0 0x73>, <&audma1 0x74>;
2038 dmas = <&audma0 0x75>, <&audma1 0x76>;
2042 dmas = <&audma0 0x79>, <&audma1 0x7a>;
2046 dmas = <&audma0 0x7b>, <&audma1 0x7c>;
2050 dmas = <&audma0 0x7d>, <&audma1 0x7e>;
2054 dmas = <&audma0 0x7F>, <&audma1 0x80>;
2058 dmas = <&audma0 0x81>, <&audma1 0x82>;
2062 dmas = <&audma0 0x83>, <&audma1 0x84>;
2066 dmas = <&audma0 0xA3>, <&audma1 0xA4>;
2070 dmas = <&audma0 0xA5>, <&audma1 0xA6>;
2074 dmas = <&audma0 0xA7>, <&audma1 0xA8>;
2078 dmas = <&audma0 0xA9>, <&audma1 0xAA>;
2084 ssi0: ssi-0 {
2086 dmas = <&audma0 0x01>, <&audma1 0x02>;
2091 dmas = <&audma0 0x03>, <&audma1 0x04>;
2096 dmas = <&audma0 0x05>, <&audma1 0x06>;
2101 dmas = <&audma0 0x07>, <&audma1 0x08>;
2106 dmas = <&audma0 0x09>, <&audma1 0x0a>;
2111 dmas = <&audma0 0x0b>, <&audma1 0x0c>;
2116 dmas = <&audma0 0x0d>, <&audma1 0x0e>;
2121 dmas = <&audma0 0x0f>, <&audma1 0x10>;
2126 dmas = <&audma0 0x11>, <&audma1 0x12>;
2131 dmas = <&audma0 0x13>, <&audma1 0x14>;
2140 reg = <0 0xec520000 0 0x800>;
2152 reg = <0 0xec700000 0 0x10000>;
2186 reg = <0 0xec720000 0 0x10000>;
2220 reg = <0 0xee000000 0 0xc00>;
2231 reg = <0 0xee020000 0 0x400>;
2241 reg = <0 0xee080000 0 0x100>;
2253 reg = <0 0xee0a0000 0 0x100>;
2265 reg = <0 0xee080100 0 0x100>;
2278 reg = <0 0xee0a0100 0 0x100>;
2292 reg = <0 0xee080200 0 0x700>;
2304 reg = <0 0xee0a0200 0 0x700>;
2315 reg = <0 0xee100000 0 0x2000>;
2329 reg = <0 0xee120000 0 0x2000>;
2343 reg = <0 0xee140000 0 0x2000>;
2357 reg = <0 0xee160000 0 0x2000>;
2371 reg = <0 0xee200000 0 0x200>,
2372 <0 0x08000000 0 0x04000000>,
2373 <0 0xee208000 0 0x100>;
2380 #size-cells = <0>;
2387 reg = <0 0xee300000 0 0x200000>;
2398 #address-cells = <0>;
2400 reg = <0x0 0xf1010000 0 0x1000>,
2401 <0x0 0xf1020000 0 0x20000>,
2402 <0x0 0xf1040000 0 0x20000>,
2403 <0x0 0xf1060000 0 0x20000>;
2415 reg = <0 0xfe000000 0 0x80000>;
2418 bus-range = <0x00 0xff>;
2420 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2421 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2422 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2423 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2425 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2430 interrupt-map-mask = <0 0 0 0>;
2431 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2436 iommu-map = <0 &ipmmu_hc 0 1>;
2437 iommu-map-mask = <0>;
2444 reg = <0 0xee800000 0 0x80000>;
2447 bus-range = <0x00 0xff>;
2449 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2450 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2451 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2452 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2454 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2459 interrupt-map-mask = <0 0 0 0>;
2460 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2465 iommu-map = <0 &ipmmu_hc 1 1>;
2466 iommu-map-mask = <0>;
2472 reg = <0 0xfe940000 0 0x2400>;
2482 reg = <0 0xfe950000 0 0x200>;
2490 reg = <0 0xfe960000 0 0x8000>;
2501 reg = <0 0xfe9a0000 0 0x8000>;
2512 reg = <0 0xfea20000 0 0x5000>;
2523 reg = <0 0xfea28000 0 0x5000>;
2534 reg = <0 0xfe96f000 0 0x200>;
2542 reg = <0 0xfea27000 0 0x200>;
2550 reg = <0 0xfea2f000 0 0x200>;
2558 reg = <0 0xfe9af000 0 0x200>;
2567 reg = <0 0xfea40000 0 0x1000>;
2576 reg = <0 0xfea50000 0 0x1000>;
2585 reg = <0 0xfea70000 0 0x1000>;
2593 reg = <0 0xfea80000 0 0x10000>;
2602 #size-cells = <0>;
2604 port@0 {
2605 reg = <0>;
2610 #size-cells = <0>;
2614 csi20vin0: endpoint@0 {
2615 reg = <0>;
2652 reg = <0 0xfeaa0000 0 0x10000>;
2661 #size-cells = <0>;
2663 port@0 {
2664 reg = <0>;
2669 #size-cells = <0>;
2673 csi40vin0: endpoint@0 {
2674 reg = <0>;
2712 reg = <0 0xfead0000 0 0x10000>;
2723 #size-cells = <0>;
2724 port@0 {
2725 reg = <0>;
2738 reg = <0 0xfeb00000 0 0x80000>;
2744 clock-names = "du.0", "du.1", "du.3";
2746 reset-names = "du.0", "du.3";
2749 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>;
2755 #size-cells = <0>;
2757 port@0 {
2758 reg = <0>;
2777 reg = <0 0xfeb90000 0 0x14>;
2785 #size-cells = <0>;
2787 port@0 {
2788 reg = <0>;
2801 reg = <0 0xfff00044 0 4>;
2809 thermal-sensors = <&tsc 0>;
2878 #clock-cells = <0>;
2879 clock-frequency = <0>;
2884 #clock-cells = <0>;
2885 clock-frequency = <0>;