Lines Matching +full:gcc +full:- +full:sm6125
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,dispcc-sm6125.h>
7 #include <dt-bindings/clock/qcom,gcc-sm6125.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/dma/qcom-gpi.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/power/qcom-rpmpd.h>
15 interrupt-parent = <&intc>;
16 #address-cells = <2>;
17 #size-cells = <2>;
22 xo_board: xo-board {
23 compatible = "fixed-clock";
24 #clock-cells = <0>;
25 clock-frequency = <19200000>;
28 sleep_clk: sleep-clk {
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 clock-frequency = <32000>;
32 clock-output-names = "sleep_clk";
37 #address-cells = <2>;
38 #size-cells = <0>;
44 enable-method = "psci";
45 capacity-dmips-mhz = <1024>;
46 next-level-cache = <&L2_0>;
47 L2_0: l2-cache {
49 cache-level = <2>;
50 cache-unified;
58 enable-method = "psci";
59 capacity-dmips-mhz = <1024>;
60 next-level-cache = <&L2_0>;
67 enable-method = "psci";
68 capacity-dmips-mhz = <1024>;
69 next-level-cache = <&L2_0>;
76 enable-method = "psci";
77 capacity-dmips-mhz = <1024>;
78 next-level-cache = <&L2_0>;
85 enable-method = "psci";
86 capacity-dmips-mhz = <1638>;
87 next-level-cache = <&L2_1>;
88 L2_1: l2-cache {
90 cache-level = <2>;
91 cache-unified;
99 enable-method = "psci";
100 capacity-dmips-mhz = <1638>;
101 next-level-cache = <&L2_1>;
108 enable-method = "psci";
109 capacity-dmips-mhz = <1638>;
110 next-level-cache = <&L2_1>;
117 enable-method = "psci";
118 capacity-dmips-mhz = <1638>;
119 next-level-cache = <&L2_1>;
122 cpu-map {
163 compatible = "qcom,scm-sm6125", "qcom,scm";
164 #reset-cells = <1>;
175 compatible = "arm,armv8-pmuv3";
180 compatible = "arm,psci-1.0";
185 compatible = "qcom,sm6125-rpm-proc", "qcom,rpm-proc";
187 glink-edge {
188 compatible = "qcom,glink-rpm";
191 qcom,rpm-msg-ram = <&rpm_msg_ram>;
194 rpm_requests: rpm-requests {
195 compatible = "qcom,rpm-sm6125";
196 qcom,glink-channels = "rpm_requests";
198 rpmcc: clock-controller {
199 compatible = "qcom,rpmcc-sm6125", "qcom,rpmcc";
200 #clock-cells = <1>;
202 clock-names = "xo";
205 rpmpd: power-controller {
206 compatible = "qcom,sm6125-rpmpd";
207 #power-domain-cells = <1>;
208 operating-points-v2 = <&rpmpd_opp_table>;
210 rpmpd_opp_table: opp-table {
211 compatible = "operating-points-v2";
214 opp-level = <RPM_SMD_LEVEL_RETENTION>;
218 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
222 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
226 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
230 opp-level = <RPM_SMD_LEVEL_SVS>;
234 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
238 opp-level = <RPM_SMD_LEVEL_NOM>;
242 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
246 opp-level = <RPM_SMD_LEVEL_TURBO>;
250 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
258 reserved_memory: reserved-memory {
259 #address-cells = <2>;
260 #size-cells = <2>;
265 no-map;
270 no-map;
275 no-map;
280 no-map;
285 no-map;
290 no-map;
295 no-map;
300 no-map;
305 no-map;
310 no-map;
315 no-map;
320 no-map;
325 no-map;
330 no-map;
335 no-map;
340 no-map;
345 no-map;
350 no-map;
355 no-map;
360 no-map;
365 no-map;
371 memory-region = <&smem_mem>;
376 #address-cells = <1>;
377 #size-cells = <1>;
379 compatible = "simple-bus";
382 compatible = "qcom,tcsr-mutex";
384 #hwlock-cells = <1>;
388 compatible = "qcom,sm6125-tlmm";
392 reg-names = "west", "south", "east";
394 gpio-controller;
395 gpio-ranges = <&tlmm 0 0 134>;
396 #gpio-cells = <2>;
397 interrupt-controller;
398 #interrupt-cells = <2>;
400 sdc2_off_state: sdc2-off-state {
401 clk-pins {
403 drive-strength = <2>;
404 bias-disable;
407 cmd-pins {
409 drive-strength = <2>;
410 bias-pull-up;
413 data-pins {
415 drive-strength = <2>;
416 bias-pull-up;
420 sdc2_on_state: sdc2-on-state {
421 clk-pins {
423 drive-strength = <16>;
424 bias-disable;
427 cmd-pins {
429 drive-strength = <10>;
430 bias-pull-up;
433 data-pins {
435 drive-strength = <10>;
436 bias-pull-up;
440 qup_i2c0_default: qup-i2c0-default-state {
443 drive-strength = <2>;
444 bias-disable;
447 qup_i2c0_sleep: qup-i2c0-sleep-state {
450 drive-strength = <2>;
451 bias-pull-up;
454 qup_i2c1_default: qup-i2c1-default-state {
457 drive-strength = <2>;
458 bias-disable;
461 qup_i2c1_sleep: qup-i2c1-sleep-state {
464 drive-strength = <2>;
465 bias-pull-up;
468 qup_i2c2_default: qup-i2c2-default-state {
471 drive-strength = <2>;
472 bias-disable;
475 qup_i2c2_sleep: qup-i2c2-sleep-state {
478 drive-strength = <2>;
479 bias-pull-up;
482 qup_i2c3_default: qup-i2c3-default-state {
485 drive-strength = <2>;
486 bias-disable;
489 qup_i2c3_sleep: qup-i2c3-sleep-state {
492 drive-strength = <2>;
493 bias-pull-up;
496 qup_i2c4_default: qup-i2c4-default-state {
499 drive-strength = <2>;
500 bias-disable;
503 qup_i2c4_sleep: qup-i2c4-sleep-state {
506 drive-strength = <2>;
507 bias-pull-up;
510 qup_i2c5_default: qup-i2c5-default-state {
513 drive-strength = <2>;
514 bias-disable;
517 qup_i2c5_sleep: qup-i2c5-sleep-state {
520 drive-strength = <2>;
521 bias-pull-up;
524 qup_i2c6_default: qup-i2c6-default-state {
527 drive-strength = <2>;
528 bias-disable;
531 qup_i2c6_sleep: qup-i2c6-sleep-state {
534 drive-strength = <2>;
535 bias-pull-up;
538 qup_i2c7_default: qup-i2c7-default-state {
541 drive-strength = <2>;
542 bias-disable;
545 qup_i2c7_sleep: qup-i2c7-sleep-state {
548 drive-strength = <2>;
549 bias-pull-up;
552 qup_i2c8_default: qup-i2c8-default-state {
555 drive-strength = <2>;
556 bias-disable;
559 qup_i2c8_sleep: qup-i2c8-sleep-state {
562 drive-strength = <2>;
563 bias-pull-up;
566 qup_i2c9_default: qup-i2c9-default-state {
569 drive-strength = <2>;
570 bias-disable;
573 qup_i2c9_sleep: qup-i2c9-sleep-state {
576 drive-strength = <2>;
577 bias-pull-up;
580 qup_spi0_default: qup-spi0-default-state {
583 drive-strength = <6>;
584 bias-disable;
587 qup_spi0_sleep: qup-spi0-sleep-state {
590 drive-strength = <6>;
591 bias-disable;
594 qup_spi2_default: qup-spi2-default-state {
597 drive-strength = <6>;
598 bias-disable;
601 qup_spi2_sleep: qup-spi2-sleep-state {
604 drive-strength = <6>;
605 bias-disable;
608 qup_spi5_default: qup-spi5-default-state {
611 drive-strength = <6>;
612 bias-disable;
615 qup_spi5_sleep: qup-spi5-sleep-state {
618 drive-strength = <6>;
619 bias-disable;
622 qup_spi6_default: qup-spi6-default-state {
625 drive-strength = <6>;
626 bias-disable;
629 qup_spi6_sleep: qup-spi6-sleep-state {
632 drive-strength = <6>;
633 bias-disable;
636 qup_spi8_default: qup-spi8-default-state {
639 drive-strength = <6>;
640 bias-disable;
643 qup_spi8_sleep: qup-spi8-sleep-state {
646 drive-strength = <6>;
647 bias-disable;
650 qup_spi9_default: qup-spi9-default-state {
653 drive-strength = <6>;
654 bias-disable;
657 qup_spi9_sleep: qup-spi9-sleep-state {
660 drive-strength = <6>;
661 bias-disable;
665 gcc: clock-controller@1400000 {
666 compatible = "qcom,gcc-sm6125";
668 #clock-cells = <1>;
669 #reset-cells = <1>;
670 #power-domain-cells = <1>;
671 clock-names = "bi_tcxo", "sleep_clk";
676 compatible = "qcom,msm8996-qusb2-phy";
678 #phy-cells = <0>;
680 clocks = <&gcc GCC_AHB2PHY_USB_CLK>,
682 clock-names = "cfg_ahb", "ref";
684 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
689 compatible = "qcom,spmi-pmic-arb";
695 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
696 interrupt-names = "periph_irq";
700 #address-cells = <2>;
701 #size-cells = <0>;
702 interrupt-controller;
703 #interrupt-cells = <4>;
707 compatible = "qcom,rpm-msg-ram";
712 compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5";
714 reg-names = "hc", "cqhci";
718 interrupt-names = "hc_irq", "pwr_irq";
720 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
721 <&gcc GCC_SDCC1_APPS_CLK>,
723 clock-names = "iface", "core", "xo";
726 power-domains = <&rpmpd SM6125_VDDCX>;
728 qcom,dll-config = <0x000f642c>;
729 qcom,ddr-config = <0x80040873>;
731 bus-width = <8>;
732 non-removable;
733 supports-cqe;
739 compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5";
741 reg-names = "hc";
745 interrupt-names = "hc_irq", "pwr_irq";
747 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
748 <&gcc GCC_SDCC2_APPS_CLK>,
750 clock-names = "iface", "core", "xo";
753 pinctrl-0 = <&sdc2_on_state>;
754 pinctrl-1 = <&sdc2_off_state>;
755 pinctrl-names = "default", "sleep";
757 power-domains = <&rpmpd SM6125_VDDCX>;
759 qcom,dll-config = <0x0007642c>;
760 qcom,ddr-config = <0x80040873>;
762 bus-width = <4>;
767 compatible = "qcom,sm6125-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
769 reg-names = "std", "ice";
772 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
773 <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>,
774 <&gcc GCC_UFS_PHY_AHB_CLK>,
775 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
777 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
778 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
779 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
780 clock-names = "core_clk",
788 freq-table-hz = <50000000 240000000>,
797 resets = <&gcc GCC_UFS_PHY_BCR>;
798 reset-names = "rst";
799 #reset-cells = <1>;
802 phy-names = "ufsphy";
804 lanes-per-direction = <1>;
812 compatible = "qcom,sm6125-qmp-ufs-phy";
815 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
816 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
817 clock-names = "ref",
821 reset-names = "ufsphy";
823 power-domains = <&gcc UFS_PHY_GDSC>;
825 #phy-cells = <0>;
830 gpi_dma0: dma-controller@4a00000 {
831 compatible = "qcom,sm6125-gpi-dma", "qcom,sdm845-gpi-dma";
841 dma-channels = <8>;
842 dma-channel-mask = <0x1f>;
844 #dma-cells = <3>;
849 compatible = "qcom,geni-se-qup";
851 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
852 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
853 clock-names = "m-ahb", "s-ahb";
855 #address-cells = <1>;
856 #size-cells = <1>;
861 compatible = "qcom,geni-i2c";
863 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
864 clock-names = "se";
866 pinctrl-0 = <&qup_i2c0_default>;
867 pinctrl-1 = <&qup_i2c0_sleep>;
868 pinctrl-names = "default", "sleep";
871 dma-names = "tx", "rx";
872 #address-cells = <1>;
873 #size-cells = <0>;
878 compatible = "qcom,geni-spi";
880 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
881 clock-names = "se";
883 pinctrl-0 = <&qup_spi0_default>;
884 pinctrl-1 = <&qup_spi0_sleep>;
885 pinctrl-names = "default", "sleep";
888 dma-names = "tx", "rx";
889 #address-cells = <1>;
890 #size-cells = <0>;
895 compatible = "qcom,geni-i2c";
897 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
898 clock-names = "se";
900 pinctrl-0 = <&qup_i2c1_default>;
901 pinctrl-1 = <&qup_i2c1_sleep>;
902 pinctrl-names = "default", "sleep";
905 dma-names = "tx", "rx";
906 #address-cells = <1>;
907 #size-cells = <0>;
912 compatible = "qcom,geni-i2c";
914 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
915 clock-names = "se";
917 pinctrl-0 = <&qup_i2c2_default>;
918 pinctrl-1 = <&qup_i2c2_sleep>;
919 pinctrl-names = "default", "sleep";
922 dma-names = "tx", "rx";
923 #address-cells = <1>;
924 #size-cells = <0>;
929 compatible = "qcom,geni-spi";
931 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
932 clock-names = "se";
934 pinctrl-0 = <&qup_spi2_default>;
935 pinctrl-1 = <&qup_spi2_sleep>;
936 pinctrl-names = "default", "sleep";
939 dma-names = "tx", "rx";
940 #address-cells = <1>;
941 #size-cells = <0>;
946 compatible = "qcom,geni-i2c";
948 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
949 clock-names = "se";
951 pinctrl-0 = <&qup_i2c3_default>;
952 pinctrl-1 = <&qup_i2c3_sleep>;
953 pinctrl-names = "default", "sleep";
956 dma-names = "tx", "rx";
957 #address-cells = <1>;
958 #size-cells = <0>;
963 compatible = "qcom,geni-i2c";
965 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
966 clock-names = "se";
968 pinctrl-0 = <&qup_i2c4_default>;
969 pinctrl-1 = <&qup_i2c4_sleep>;
970 pinctrl-names = "default", "sleep";
973 dma-names = "tx", "rx";
974 #address-cells = <1>;
975 #size-cells = <0>;
980 gpi_dma1: dma-controller@4c00000 {
981 compatible = "qcom,sm6125-gpi-dma", "qcom,sdm845-gpi-dma";
991 dma-channels = <8>;
992 dma-channel-mask = <0x0f>;
994 #dma-cells = <3>;
999 compatible = "qcom,geni-se-qup";
1001 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1002 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1003 clock-names = "m-ahb", "s-ahb";
1005 #address-cells = <1>;
1006 #size-cells = <1>;
1011 compatible = "qcom,geni-i2c";
1013 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1014 clock-names = "se";
1016 pinctrl-0 = <&qup_i2c5_default>;
1017 pinctrl-1 = <&qup_i2c5_sleep>;
1018 pinctrl-names = "default", "sleep";
1021 dma-names = "tx", "rx";
1022 #address-cells = <1>;
1023 #size-cells = <0>;
1028 compatible = "qcom,geni-spi";
1030 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1031 clock-names = "se";
1033 pinctrl-0 = <&qup_spi5_default>;
1034 pinctrl-1 = <&qup_spi5_sleep>;
1035 pinctrl-names = "default", "sleep";
1038 dma-names = "tx", "rx";
1039 #address-cells = <1>;
1040 #size-cells = <0>;
1045 compatible = "qcom,geni-i2c";
1047 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1048 clock-names = "se";
1050 pinctrl-0 = <&qup_i2c6_default>;
1051 pinctrl-1 = <&qup_i2c6_sleep>;
1052 pinctrl-names = "default", "sleep";
1055 dma-names = "tx", "rx";
1056 #address-cells = <1>;
1057 #size-cells = <0>;
1062 compatible = "qcom,geni-spi";
1064 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1065 clock-names = "se";
1067 pinctrl-0 = <&qup_spi6_default>;
1068 pinctrl-1 = <&qup_spi6_sleep>;
1069 pinctrl-names = "default", "sleep";
1072 dma-names = "tx", "rx";
1073 #address-cells = <1>;
1074 #size-cells = <0>;
1079 compatible = "qcom,geni-i2c";
1081 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1082 clock-names = "se";
1084 pinctrl-0 = <&qup_i2c7_default>;
1085 pinctrl-1 = <&qup_i2c7_sleep>;
1086 pinctrl-names = "default", "sleep";
1089 dma-names = "tx", "rx";
1090 #address-cells = <1>;
1091 #size-cells = <0>;
1096 compatible = "qcom,geni-i2c";
1098 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1099 clock-names = "se";
1101 pinctrl-0 = <&qup_i2c8_default>;
1102 pinctrl-1 = <&qup_i2c8_sleep>;
1103 pinctrl-names = "default", "sleep";
1106 dma-names = "tx", "rx";
1107 #address-cells = <1>;
1108 #size-cells = <0>;
1113 compatible = "qcom,geni-spi";
1115 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1116 clock-names = "se";
1118 pinctrl-0 = <&qup_spi8_default>;
1119 pinctrl-1 = <&qup_spi8_sleep>;
1120 pinctrl-names = "default", "sleep";
1123 dma-names = "tx", "rx";
1124 #address-cells = <1>;
1125 #size-cells = <0>;
1130 compatible = "qcom,geni-i2c";
1132 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1133 clock-names = "se";
1135 pinctrl-0 = <&qup_i2c9_default>;
1136 pinctrl-1 = <&qup_i2c9_sleep>;
1137 pinctrl-names = "default", "sleep";
1140 dma-names = "tx", "rx";
1141 #address-cells = <1>;
1142 #size-cells = <0>;
1147 compatible = "qcom,geni-spi";
1149 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1150 clock-names = "se";
1152 pinctrl-0 = <&qup_spi9_default>;
1153 pinctrl-1 = <&qup_spi9_sleep>;
1154 pinctrl-names = "default", "sleep";
1157 dma-names = "tx", "rx";
1158 #address-cells = <1>;
1159 #size-cells = <0>;
1165 compatible = "qcom,sm6125-dwc3", "qcom,dwc3";
1167 #address-cells = <1>;
1168 #size-cells = <1>;
1171 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1172 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1173 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
1174 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
1175 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1176 <&gcc GCC_USB3_PRIM_CLKREF_CLK>;
1177 clock-names = "cfg_noc",
1184 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1185 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
1186 assigned-clock-rates = <19200000>, <66666667>;
1190 interrupt-names = "hs_phy_irq", "ss_phy_irq";
1192 power-domains = <&gcc USB30_PRIM_GDSC>;
1193 qcom,select-utmi-as-pipe-clk;
1202 phy-names = "usb2-phy";
1205 maximum-speed = "high-speed";
1211 compatible = "qcom,rpm-stats";
1215 mdss: display-subsystem@5e00000 {
1216 compatible = "qcom,sm6125-mdss";
1218 reg-names = "mdss";
1221 interrupt-controller;
1222 #interrupt-cells = <1>;
1224 clocks = <&gcc GCC_DISP_AHB_CLK>,
1227 clock-names = "iface",
1231 power-domains = <&dispcc MDSS_GDSC>;
1235 #address-cells = <1>;
1236 #size-cells = <1>;
1241 mdss_mdp: display-controller@5e01000 {
1242 compatible = "qcom,sm6125-dpu";
1245 reg-names = "mdp", "vbif";
1247 interrupt-parent = <&mdss>;
1250 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
1256 <&gcc GCC_DISP_THROTTLE_CORE_CLK>;
1257 clock-names = "bus",
1264 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
1265 assigned-clock-rates = <19200000>;
1267 operating-points-v2 = <&mdp_opp_table>;
1268 power-domains = <&rpmpd SM6125_VDDCX>;
1271 #address-cells = <1>;
1272 #size-cells = <0>;
1277 remote-endpoint = <&mdss_dsi0_in>;
1282 mdp_opp_table: opp-table {
1283 compatible = "operating-points-v2";
1285 opp-192000000 {
1286 opp-hz = /bits/ 64 <192000000>;
1287 required-opps = <&rpmpd_opp_low_svs>;
1290 opp-256000000 {
1291 opp-hz = /bits/ 64 <256000000>;
1292 required-opps = <&rpmpd_opp_svs>;
1295 opp-307200000 {
1296 opp-hz = /bits/ 64 <307200000>;
1297 required-opps = <&rpmpd_opp_svs_plus>;
1300 opp-384000000 {
1301 opp-hz = /bits/ 64 <384000000>;
1302 required-opps = <&rpmpd_opp_nom>;
1305 opp-400000000 {
1306 opp-hz = /bits/ 64 <400000000>;
1307 required-opps = <&rpmpd_opp_turbo>;
1313 compatible = "qcom,sm6125-dsi-ctrl", "qcom,mdss-dsi-ctrl";
1315 reg-names = "dsi_ctrl";
1317 interrupt-parent = <&mdss>;
1325 <&gcc GCC_DISP_HF_AXI_CLK>;
1326 clock-names = "byte",
1332 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
1334 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
1336 operating-points-v2 = <&dsi_opp_table>;
1337 power-domains = <&rpmpd SM6125_VDDCX>;
1340 phy-names = "dsi";
1342 #address-cells = <1>;
1343 #size-cells = <0>;
1348 #address-cells = <1>;
1349 #size-cells = <0>;
1354 remote-endpoint = <&dpu_intf1_out>;
1365 dsi_opp_table: opp-table {
1366 compatible = "operating-points-v2";
1368 opp-164000000 {
1369 opp-hz = /bits/ 64 <164000000>;
1370 required-opps = <&rpmpd_opp_low_svs>;
1373 opp-187500000 {
1374 opp-hz = /bits/ 64 <187500000>;
1375 required-opps = <&rpmpd_opp_svs>;
1381 compatible = "qcom,sm6125-dsi-phy-14nm";
1385 reg-names = "dsi_phy",
1389 #clock-cells = <1>;
1390 #phy-cells = <0>;
1394 clock-names = "iface",
1397 required-opps = <&rpmpd_opp_nom>;
1398 power-domains = <&rpmpd SM6125_VDDMX>;
1404 dispcc: clock-controller@5f00000 {
1405 compatible = "qcom,sm6125-dispcc";
1414 <&gcc GCC_DISP_AHB_CLK>,
1415 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
1416 clock-names = "bi_tcxo",
1425 required-opps = <&rpmpd_opp_ret>;
1426 power-domains = <&rpmpd SM6125_VDDCX>;
1428 #clock-cells = <1>;
1429 #power-domain-cells = <1>;
1433 compatible = "qcom,sm6125-smmu-500", "qcom,smmu-500", "arm,mmu-500";
1501 #global-interrupts = <1>;
1502 #iommu-cells = <2>;
1506 compatible = "qcom,sm6125-apcs-hmss-global",
1507 "qcom,msm8994-apcs-kpss-global";
1510 #mbox-cells = <1>;
1514 compatible = "arm,armv7-timer-mem";
1515 #address-cells = <1>;
1516 #size-cells = <1>;
1519 clock-frequency = <19200000>;
1522 frame-number = <0>;
1530 frame-number = <1>;
1537 frame-number = <2>;
1544 frame-number = <3>;
1551 frame-number = <4>;
1558 frame-number = <5>;
1565 frame-number = <6>;
1572 intc: interrupt-controller@f200000 {
1573 compatible = "arm,gic-v3";
1576 #interrupt-cells = <3>;
1577 interrupt-controller;
1583 compatible = "arm,armv8-timer";
1588 clock-frequency = <19200000>;