Lines Matching +full:mmu +full:- +full:500
1 // SPDX-License-Identifier: BSD-3-Clause
9 #include <dt-bindings/clock/qcom,rpmh.h>
10 #include <dt-bindings/clock/qcom,sdx75-gcc.h>
11 #include <dt-bindings/interconnect/qcom,icc.h>
12 #include <dt-bindings/interconnect/qcom,sdx75.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/power/qcom,rpmhpd.h>
15 #include <dt-bindings/power/qcom-rpmpd.h>
16 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
19 #address-cells = <2>;
20 #size-cells = <2>;
21 interrupt-parent = <&intc>;
26 xo_board: xo-board {
27 compatible = "fixed-clock";
28 clock-frequency = <76800000>;
29 #clock-cells = <0>;
32 sleep_clk: sleep-clk {
33 compatible = "fixed-clock";
34 clock-frequency = <32000>;
35 #clock-cells = <0>;
40 #address-cells = <2>;
41 #size-cells = <0>;
45 compatible = "arm,cortex-a55";
48 enable-method = "psci";
49 power-domains = <&CPU_PD0>;
50 power-domain-names = "psci";
51 qcom,freq-domain = <&cpufreq_hw 0>;
52 capacity-dmips-mhz = <1024>;
53 dynamic-power-coefficient = <100>;
54 next-level-cache = <&L2_0>;
56 L2_0: l2-cache {
58 cache-level = <2>;
59 cache-unified;
60 next-level-cache = <&L3_0>;
61 L3_0: l3-cache {
63 cache-level = <3>;
64 cache-unified;
71 compatible = "arm,cortex-a55";
74 enable-method = "psci";
75 power-domains = <&CPU_PD1>;
76 power-domain-names = "psci";
77 qcom,freq-domain = <&cpufreq_hw 0>;
78 capacity-dmips-mhz = <1024>;
79 dynamic-power-coefficient = <100>;
80 next-level-cache = <&L2_100>;
82 L2_100: l2-cache {
84 cache-level = <2>;
85 cache-unified;
86 next-level-cache = <&L3_0>;
92 compatible = "arm,cortex-a55";
95 enable-method = "psci";
96 power-domains = <&CPU_PD2>;
97 power-domain-names = "psci";
98 qcom,freq-domain = <&cpufreq_hw 0>;
99 capacity-dmips-mhz = <1024>;
100 dynamic-power-coefficient = <100>;
101 next-level-cache = <&L2_200>;
103 L2_200: l2-cache {
105 cache-level = <2>;
106 cache-unified;
107 next-level-cache = <&L3_0>;
113 compatible = "arm,cortex-a55";
116 enable-method = "psci";
117 power-domains = <&CPU_PD3>;
118 power-domain-names = "psci";
119 qcom,freq-domain = <&cpufreq_hw 0>;
120 capacity-dmips-mhz = <1024>;
121 dynamic-power-coefficient = <100>;
122 next-level-cache = <&L2_300>;
124 L2_300: l2-cache {
126 cache-level = <2>;
127 cache-unified;
128 next-level-cache = <&L3_0>;
132 cpu-map {
152 idle-states {
153 entry-method = "psci";
155 CPU_OFF: cpu-sleep-0 {
156 compatible = "arm,idle-state";
157 entry-latency-us = <235>;
158 exit-latency-us = <428>;
159 min-residency-us = <1774>;
160 arm,psci-suspend-param = <0x40000003>;
161 local-timer-stop;
164 CPU_RAIL_OFF: cpu-rail-sleep-1 {
165 compatible = "arm,idle-state";
166 entry-latency-us = <800>;
167 exit-latency-us = <750>;
168 min-residency-us = <4090>;
169 arm,psci-suspend-param = <0x40000004>;
170 local-timer-stop;
175 domain-idle-states {
176 CLUSTER_SLEEP_0: cluster-sleep-0 {
177 compatible = "domain-idle-state";
178 arm,psci-suspend-param = <0x41000044>;
179 entry-latency-us = <1050>;
180 exit-latency-us = <2500>;
181 min-residency-us = <5309>;
184 CLUSTER_SLEEP_1: cluster-sleep-1 {
185 compatible = "domain-idle-state";
186 arm,psci-suspend-param = <0x41001344>;
187 entry-latency-us = <2761>;
188 exit-latency-us = <3964>;
189 min-residency-us = <8467>;
192 CLUSTER_SLEEP_2: cluster-sleep-2 {
193 compatible = "domain-idle-state";
194 arm,psci-suspend-param = <0x4100b344>;
195 entry-latency-us = <2793>;
196 exit-latency-us = <4023>;
197 min-residency-us = <9826>;
204 compatible = "qcom,scm-sdx75", "qcom,scm";
208 clk_virt: interconnect-0 {
209 compatible = "qcom,sdx75-clk-virt";
210 #interconnect-cells = <2>;
211 qcom,bcm-voters = <&apps_bcm_voter>;
215 mc_virt: interconnect-1 {
216 compatible = "qcom,sdx75-mc-virt";
217 #interconnect-cells = <2>;
218 qcom,bcm-voters = <&apps_bcm_voter>;
227 compatible = "arm,armv8-pmuv3";
232 compatible = "arm,psci-1.0";
235 CPU_PD0: power-domain-cpu0 {
236 #power-domain-cells = <0>;
237 power-domains = <&CLUSTER_PD>;
238 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
241 CPU_PD1: power-domain-cpu1 {
242 #power-domain-cells = <0>;
243 power-domains = <&CLUSTER_PD>;
244 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
247 CPU_PD2: power-domain-cpu2 {
248 #power-domain-cells = <0>;
249 power-domains = <&CLUSTER_PD>;
250 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
253 CPU_PD3: power-domain-cpu3 {
254 #power-domain-cells = <0>;
255 power-domains = <&CLUSTER_PD>;
256 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
259 CLUSTER_PD: power-domain-cpu-cluster0 {
260 #power-domain-cells = <0>;
261 domain-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1 &CLUSTER_SLEEP_2>;
265 reserved-memory {
266 #address-cells = <2>;
267 #size-cells = <2>;
270 gunyah_hyp_mem: gunyah-hyp@80000000 {
272 no-map;
275 hyp_elf_package_mem: hyp-elf-package@80800000 {
277 no-map;
280 access_control_db_mem: access-control-db@81380000 {
282 no-map;
287 no-map;
290 trusted_apps_mem: trusted-apps@81780000 {
292 no-map;
295 xbl_ramdump_mem: xbl-ramdump@87a00000 {
297 no-map;
300 cpucp_fw_mem: cpucp-fw@87c00000 {
302 no-map;
305 xbl_dtlog_mem: xbl-dtlog@87d00000 {
307 no-map;
310 xbl_sc_mem: xbl-sc@87d40000 {
312 no-map;
315 modem_efs_shared_mem: modem-efs-shared@87d80000 {
317 no-map;
320 aop_image_mem: aop-image@87e00000 {
322 no-map;
327 no-map;
330 aop_cmd_db_mem: aop-cmd-db@87ee0000 {
331 compatible = "qcom,cmd-db";
333 no-map;
336 aop_config_mem: aop-config@87f00000 {
338 no-map;
341 ipa_fw_mem: ipa-fw@87f20000 {
343 no-map;
348 no-map;
351 tme_crashdump_mem: tme-crashdump@87f31000 {
353 no-map;
356 tme_log_mem: tme-log@87f71000 {
358 no-map;
361 uefi_log_mem: uefi-log@87f75000 {
363 no-map;
368 no-map;
371 audio_heap_mem: audio-heap@88b00000 {
372 compatible = "shared-dma-pool";
374 no-map;
377 mpss_dsmharq_mem: mpss-dsmharq@88f00000 {
379 no-map;
382 q6_mpss_dtb_mem: q6-mpss-dtb@8df80000 {
384 no-map;
389 no-map;
392 gunyah_trace_buffer_mem: gunyah-trace-buffer@bdb00000 {
394 no-map;
397 smmu_debug_buf_mem: smmu-debug-buf@bfb00000 {
399 no-map;
402 hyp_smmu_s2_pt_mem: hyp-smmu-s2-pt@bfc00000 {
404 no-map;
410 memory-region = <&smem_mem>;
415 compatible = "simple-bus";
416 #address-cells = <2>;
417 #size-cells = <2>;
419 dma-ranges = <0 0 0 0 0x10 0>;
421 gcc: clock-controller@80000 {
422 compatible = "qcom,sdx75-gcc";
439 #clock-cells = <1>;
440 #reset-cells = <1>;
441 #power-domain-cells = <1>;
445 compatible = "qcom,geni-se-qup";
449 clock-names = "m-ahb",
450 "s-ahb";
454 interconnect-names = "qup-core";
455 #address-cells = <2>;
456 #size-cells = <2>;
461 compatible = "qcom,geni-debug-uart";
464 clock-names = "se";
469 interconnect-names = "qup-core",
470 "qup-config";
472 pinctrl-0 = <&qupv3_se1_2uart_active>;
473 pinctrl-1 = <&qupv3_se1_2uart_sleep>;
474 pinctrl-names = "default",
481 compatible = "qcom,sdx75-snps-eusb2-phy", "qcom,sm8550-snps-eusb2-phy";
483 #phy-cells = <0>;
486 clock-names = "ref";
494 compatible = "qcom,sdx75-qmp-usb3-uni-phy";
501 clock-names = "aux",
506 power-domains = <&gcc GCC_USB3_PHY_GDSC>;
510 reset-names = "phy",
513 #clock-cells = <0>;
514 clock-output-names = "usb3_uni_phy_pipe_clk_src";
516 #phy-cells = <0>;
522 compatible = "qcom,sdx75-system-noc";
524 #interconnect-cells = <2>;
525 qcom,bcm-voters = <&apps_bcm_voter>;
529 compatible = "qcom,sdx75-pcie-anoc";
531 #interconnect-cells = <2>;
532 qcom,bcm-voters = <&apps_bcm_voter>;
536 compatible = "qcom,tcsr-mutex";
538 #hwlock-cells = <1>;
542 compatible = "qcom,sdx75-dwc3", "qcom,dwc3";
544 #address-cells = <2>;
545 #size-cells = <2>;
553 clock-names = "cfg_noc",
559 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
561 assigned-clock-rates = <19200000>, <200000000>;
563 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
567 interrupt-names = "hs_phy_irq",
572 power-domains = <&gcc GCC_USB30_GDSC>;
580 interconnect-names = "usb-ddr",
581 "apps-usb";
594 phy-names = "usb2-phy",
595 "usb3-phy";
598 #address-cells = <1>;
599 #size-cells = <0>;
618 pdc: interrupt-controller@b220000 {
619 compatible = "qcom,sdx75-pdc", "qcom,pdc";
622 qcom,pdc-ranges = <0 147 52>,
624 <84 500 59>;
625 #interrupt-cells = <2>;
626 interrupt-parent = <&intc>;
627 interrupt-controller;
631 compatible = "qcom,spmi-pmic-arb";
637 reg-names = "core",
642 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
643 interrupt-names = "periph_irq";
646 qcom,bus-id = <0>;
647 #address-cells = <2>;
648 #size-cells = <0>;
649 interrupt-controller;
650 #interrupt-cells = <4>;
654 compatible = "qcom,sdx75-tlmm";
657 gpio-controller;
658 #gpio-cells = <2>;
659 gpio-ranges = <&tlmm 0 0 133>;
660 interrupt-controller;
661 #interrupt-cells = <2>;
662 wakeup-parent = <&pdc>;
664 qupv3_se1_2uart_active: qupv3-se1-2uart-active-state {
665 tx-pins {
668 drive-strength = <2>;
669 bias-disable;
672 rx-pins {
675 drive-strength = <2>;
676 bias-disable;
680 qupv3_se1_2uart_sleep: qupv3-se1-2uart-sleep-state {
683 drive-strength = <2>;
684 bias-pull-down;
689 compatible = "qcom,sdx75-smmu-500", "qcom,smmu-500", "arm,mmu-500";
691 #iommu-cells = <2>;
692 #global-interrupts = <2>;
693 dma-coherent;
729 intc: interrupt-controller@17200000 {
730 compatible = "arm,gic-v3";
731 #interrupt-cells = <3>;
732 interrupt-controller;
733 #redistributor-regions = <1>;
734 redistributor-stride = <0x0 0x20000>;
741 compatible = "arm,armv7-timer-mem";
743 #address-cells = <1>;
744 #size-cells = <1>;
750 frame-number = <0>;
757 frame-number = <1>;
764 frame-number = <2>;
771 frame-number = <3>;
778 frame-number = <4>;
785 frame-number = <5>;
792 frame-number = <6>;
800 compatible = "qcom,rpmh-rsc";
804 reg-names = "drv-0", "drv-1", "drv-2";
809 power-domains = <&CLUSTER_PD>;
810 qcom,tcs-offset = <0xd00>;
811 qcom,drv-id = <2>;
812 qcom,tcs-config = <ACTIVE_TCS 3>,
817 apps_bcm_voter: bcm-voter {
818 compatible = "qcom,bcm-voter";
821 rpmhcc: clock-controller {
822 compatible = "qcom,sdx75-rpmh-clk";
824 clock-names = "xo";
825 #clock-cells = <1>;
828 rpmhpd: power-controller {
829 compatible = "qcom,sdx75-rpmhpd";
830 #power-domain-cells = <1>;
831 operating-points-v2 = <&rpmhpd_opp_table>;
833 rpmhpd_opp_table: opp-table {
834 compatible = "operating-points-v2";
836 rpmhpd_opp_ret: opp-16 {
837 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
840 rpmhpd_opp_min_svs: opp-48 {
841 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
844 rpmhpd_opp_low_svs: opp-64 {
845 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
848 rpmhpd_opp_svs: opp-128 {
849 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
852 rpmhpd_opp_svs_l1: opp-192 {
853 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
856 rpmhpd_opp_nom: opp-256 {
857 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
860 rpmhpd_opp_nom_l1: opp-320 {
861 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
864 rpmhpd_opp_nom_l2: opp-336 {
865 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
868 rpmhpd_opp_turbo: opp-384 {
869 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
872 rpmhpd_opp_turbo_l1: opp-416 {
873 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
880 compatible = "qcom,sdx75-cpufreq-epss", "qcom,cpufreq-epss";
882 reg-names = "freq-domain0";
885 clock-names = "xo",
888 interrupt-names = "dcvsh-irq-0";
889 #freq-domain-cells = <1>;
890 #clock-cells = <1>;
894 compatible = "qcom,sdx75-dc-noc";
896 #interconnect-cells = <2>;
897 qcom,bcm-voters = <&apps_bcm_voter>;
901 compatible = "qcom,sdx75-gem-noc";
903 #interconnect-cells = <2>;
904 qcom,bcm-voters = <&apps_bcm_voter>;
909 compatible = "arm,armv8-timer";