Lines Matching +full:opp +full:- +full:202000000
1 // SPDX-License-Identifier: BSD-3-Clause
7 #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
8 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
9 #include <dt-bindings/clock/qcom,gpucc-sc8280xp.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/clock/qcom,sc8280xp-camcc.h>
12 #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
13 #include <dt-bindings/interconnect/qcom,osm-l3.h>
14 #include <dt-bindings/interconnect/qcom,sc8280xp.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/phy/phy-qcom-qmp.h>
18 #include <dt-bindings/power/qcom-rpmpd.h>
19 #include <dt-bindings/soc/qcom,gpr.h>
20 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
21 #include <dt-bindings/sound/qcom,q6afe.h>
22 #include <dt-bindings/thermal/thermal.h>
25 interrupt-parent = <&intc>;
27 #address-cells = <2>;
28 #size-cells = <2>;
31 xo_board_clk: xo-board-clk {
32 compatible = "fixed-clock";
33 #clock-cells = <0>;
36 sleep_clk: sleep-clk {
37 compatible = "fixed-clock";
38 #clock-cells = <0>;
39 clock-frequency = <32764>;
44 #address-cells = <2>;
45 #size-cells = <0>;
49 compatible = "arm,cortex-a78c";
52 enable-method = "psci";
53 capacity-dmips-mhz = <602>;
54 next-level-cache = <&L2_0>;
55 power-domains = <&CPU_PD0>;
56 power-domain-names = "psci";
57 qcom,freq-domain = <&cpufreq_hw 0>;
58 operating-points-v2 = <&cpu0_opp_table>;
60 #cooling-cells = <2>;
61 L2_0: l2-cache {
63 cache-level = <2>;
64 cache-unified;
65 next-level-cache = <&L3_0>;
66 L3_0: l3-cache {
68 cache-level = <3>;
69 cache-unified;
76 compatible = "arm,cortex-a78c";
79 enable-method = "psci";
80 capacity-dmips-mhz = <602>;
81 next-level-cache = <&L2_100>;
82 power-domains = <&CPU_PD1>;
83 power-domain-names = "psci";
84 qcom,freq-domain = <&cpufreq_hw 0>;
85 operating-points-v2 = <&cpu0_opp_table>;
87 #cooling-cells = <2>;
88 L2_100: l2-cache {
90 cache-level = <2>;
91 cache-unified;
92 next-level-cache = <&L3_0>;
98 compatible = "arm,cortex-a78c";
101 enable-method = "psci";
102 capacity-dmips-mhz = <602>;
103 next-level-cache = <&L2_200>;
104 power-domains = <&CPU_PD2>;
105 power-domain-names = "psci";
106 qcom,freq-domain = <&cpufreq_hw 0>;
107 operating-points-v2 = <&cpu0_opp_table>;
109 #cooling-cells = <2>;
110 L2_200: l2-cache {
112 cache-level = <2>;
113 cache-unified;
114 next-level-cache = <&L3_0>;
120 compatible = "arm,cortex-a78c";
123 enable-method = "psci";
124 capacity-dmips-mhz = <602>;
125 next-level-cache = <&L2_300>;
126 power-domains = <&CPU_PD3>;
127 power-domain-names = "psci";
128 qcom,freq-domain = <&cpufreq_hw 0>;
129 operating-points-v2 = <&cpu0_opp_table>;
131 #cooling-cells = <2>;
132 L2_300: l2-cache {
134 cache-level = <2>;
135 cache-unified;
136 next-level-cache = <&L3_0>;
142 compatible = "arm,cortex-x1c";
145 enable-method = "psci";
146 capacity-dmips-mhz = <1024>;
147 next-level-cache = <&L2_400>;
148 power-domains = <&CPU_PD4>;
149 power-domain-names = "psci";
150 qcom,freq-domain = <&cpufreq_hw 1>;
151 operating-points-v2 = <&cpu4_opp_table>;
153 #cooling-cells = <2>;
154 L2_400: l2-cache {
156 cache-level = <2>;
157 cache-unified;
158 next-level-cache = <&L3_0>;
164 compatible = "arm,cortex-x1c";
167 enable-method = "psci";
168 capacity-dmips-mhz = <1024>;
169 next-level-cache = <&L2_500>;
170 power-domains = <&CPU_PD5>;
171 power-domain-names = "psci";
172 qcom,freq-domain = <&cpufreq_hw 1>;
173 operating-points-v2 = <&cpu4_opp_table>;
175 #cooling-cells = <2>;
176 L2_500: l2-cache {
178 cache-level = <2>;
179 cache-unified;
180 next-level-cache = <&L3_0>;
186 compatible = "arm,cortex-x1c";
189 enable-method = "psci";
190 capacity-dmips-mhz = <1024>;
191 next-level-cache = <&L2_600>;
192 power-domains = <&CPU_PD6>;
193 power-domain-names = "psci";
194 qcom,freq-domain = <&cpufreq_hw 1>;
195 operating-points-v2 = <&cpu4_opp_table>;
197 #cooling-cells = <2>;
198 L2_600: l2-cache {
200 cache-level = <2>;
201 cache-unified;
202 next-level-cache = <&L3_0>;
208 compatible = "arm,cortex-x1c";
211 enable-method = "psci";
212 capacity-dmips-mhz = <1024>;
213 next-level-cache = <&L2_700>;
214 power-domains = <&CPU_PD7>;
215 power-domain-names = "psci";
216 qcom,freq-domain = <&cpufreq_hw 1>;
217 operating-points-v2 = <&cpu4_opp_table>;
219 #cooling-cells = <2>;
220 L2_700: l2-cache {
222 cache-level = <2>;
223 cache-unified;
224 next-level-cache = <&L3_0>;
228 cpu-map {
264 idle-states {
265 entry-method = "psci";
267 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
268 compatible = "arm,idle-state";
269 idle-state-name = "little-rail-power-collapse";
270 arm,psci-suspend-param = <0x40000004>;
271 entry-latency-us = <355>;
272 exit-latency-us = <909>;
273 min-residency-us = <3934>;
274 local-timer-stop;
277 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
278 compatible = "arm,idle-state";
279 idle-state-name = "big-rail-power-collapse";
280 arm,psci-suspend-param = <0x40000004>;
281 entry-latency-us = <241>;
282 exit-latency-us = <1461>;
283 min-residency-us = <4488>;
284 local-timer-stop;
288 domain-idle-states {
289 CLUSTER_SLEEP_0: cluster-sleep-0 {
290 compatible = "domain-idle-state";
291 arm,psci-suspend-param = <0x4100c344>;
292 entry-latency-us = <3263>;
293 exit-latency-us = <6562>;
294 min-residency-us = <9987>;
301 compatible = "qcom,scm-sc8280xp", "qcom,scm";
306 aggre1_noc: interconnect-aggre1-noc {
307 compatible = "qcom,sc8280xp-aggre1-noc";
308 #interconnect-cells = <2>;
309 qcom,bcm-voters = <&apps_bcm_voter>;
312 aggre2_noc: interconnect-aggre2-noc {
313 compatible = "qcom,sc8280xp-aggre2-noc";
314 #interconnect-cells = <2>;
315 qcom,bcm-voters = <&apps_bcm_voter>;
318 clk_virt: interconnect-clk-virt {
319 compatible = "qcom,sc8280xp-clk-virt";
320 #interconnect-cells = <2>;
321 qcom,bcm-voters = <&apps_bcm_voter>;
324 config_noc: interconnect-config-noc {
325 compatible = "qcom,sc8280xp-config-noc";
326 #interconnect-cells = <2>;
327 qcom,bcm-voters = <&apps_bcm_voter>;
330 dc_noc: interconnect-dc-noc {
331 compatible = "qcom,sc8280xp-dc-noc";
332 #interconnect-cells = <2>;
333 qcom,bcm-voters = <&apps_bcm_voter>;
336 gem_noc: interconnect-gem-noc {
337 compatible = "qcom,sc8280xp-gem-noc";
338 #interconnect-cells = <2>;
339 qcom,bcm-voters = <&apps_bcm_voter>;
342 lpass_noc: interconnect-lpass-ag-noc {
343 compatible = "qcom,sc8280xp-lpass-ag-noc";
344 #interconnect-cells = <2>;
345 qcom,bcm-voters = <&apps_bcm_voter>;
348 mc_virt: interconnect-mc-virt {
349 compatible = "qcom,sc8280xp-mc-virt";
350 #interconnect-cells = <2>;
351 qcom,bcm-voters = <&apps_bcm_voter>;
354 mmss_noc: interconnect-mmss-noc {
355 compatible = "qcom,sc8280xp-mmss-noc";
356 #interconnect-cells = <2>;
357 qcom,bcm-voters = <&apps_bcm_voter>;
360 nspa_noc: interconnect-nspa-noc {
361 compatible = "qcom,sc8280xp-nspa-noc";
362 #interconnect-cells = <2>;
363 qcom,bcm-voters = <&apps_bcm_voter>;
366 nspb_noc: interconnect-nspb-noc {
367 compatible = "qcom,sc8280xp-nspb-noc";
368 #interconnect-cells = <2>;
369 qcom,bcm-voters = <&apps_bcm_voter>;
372 system_noc: interconnect-system-noc {
373 compatible = "qcom,sc8280xp-system-noc";
374 #interconnect-cells = <2>;
375 qcom,bcm-voters = <&apps_bcm_voter>;
384 cpu0_opp_table: opp-table-cpu0 {
385 compatible = "operating-points-v2";
386 opp-shared;
388 opp-300000000 {
389 opp-hz = /bits/ 64 <300000000>;
390 opp-peak-kBps = <(300000 * 32)>;
392 opp-403200000 {
393 opp-hz = /bits/ 64 <403200000>;
394 opp-peak-kBps = <(384000 * 32)>;
396 opp-499200000 {
397 opp-hz = /bits/ 64 <499200000>;
398 opp-peak-kBps = <(480000 * 32)>;
400 opp-595200000 {
401 opp-hz = /bits/ 64 <595200000>;
402 opp-peak-kBps = <(576000 * 32)>;
404 opp-691200000 {
405 opp-hz = /bits/ 64 <691200000>;
406 opp-peak-kBps = <(672000 * 32)>;
408 opp-806400000 {
409 opp-hz = /bits/ 64 <806400000>;
410 opp-peak-kBps = <(768000 * 32)>;
412 opp-902400000 {
413 opp-hz = /bits/ 64 <902400000>;
414 opp-peak-kBps = <(864000 * 32)>;
416 opp-1017600000 {
417 opp-hz = /bits/ 64 <1017600000>;
418 opp-peak-kBps = <(960000 * 32)>;
420 opp-1113600000 {
421 opp-hz = /bits/ 64 <1113600000>;
422 opp-peak-kBps = <(1075200 * 32)>;
424 opp-1209600000 {
425 opp-hz = /bits/ 64 <1209600000>;
426 opp-peak-kBps = <(1171200 * 32)>;
428 opp-1324800000 {
429 opp-hz = /bits/ 64 <1324800000>;
430 opp-peak-kBps = <(1267200 * 32)>;
432 opp-1440000000 {
433 opp-hz = /bits/ 64 <1440000000>;
434 opp-peak-kBps = <(1363200 * 32)>;
436 opp-1555200000 {
437 opp-hz = /bits/ 64 <1555200000>;
438 opp-peak-kBps = <(1536000 * 32)>;
440 opp-1670400000 {
441 opp-hz = /bits/ 64 <1670400000>;
442 opp-peak-kBps = <(1612800 * 32)>;
444 opp-1785600000 {
445 opp-hz = /bits/ 64 <1785600000>;
446 opp-peak-kBps = <(1689600 * 32)>;
448 opp-1881600000 {
449 opp-hz = /bits/ 64 <1881600000>;
450 opp-peak-kBps = <(1689600 * 32)>;
452 opp-1996800000 {
453 opp-hz = /bits/ 64 <1996800000>;
454 opp-peak-kBps = <(1689600 * 32)>;
456 opp-2112000000 {
457 opp-hz = /bits/ 64 <2112000000>;
458 opp-peak-kBps = <(1689600 * 32)>;
460 opp-2227200000 {
461 opp-hz = /bits/ 64 <2227200000>;
462 opp-peak-kBps = <(1689600 * 32)>;
464 opp-2342400000 {
465 opp-hz = /bits/ 64 <2342400000>;
466 opp-peak-kBps = <(1689600 * 32)>;
468 opp-2438400000 {
469 opp-hz = /bits/ 64 <2438400000>;
470 opp-peak-kBps = <(1689600 * 32)>;
474 cpu4_opp_table: opp-table-cpu4 {
475 compatible = "operating-points-v2";
476 opp-shared;
478 opp-825600000 {
479 opp-hz = /bits/ 64 <825600000>;
480 opp-peak-kBps = <(768000 * 32)>;
482 opp-940800000 {
483 opp-hz = /bits/ 64 <940800000>;
484 opp-peak-kBps = <(864000 * 32)>;
486 opp-1056000000 {
487 opp-hz = /bits/ 64 <1056000000>;
488 opp-peak-kBps = <(960000 * 32)>;
490 opp-1171200000 {
491 opp-hz = /bits/ 64 <1171200000>;
492 opp-peak-kBps = <(1171200 * 32)>;
494 opp-1286400000 {
495 opp-hz = /bits/ 64 <1286400000>;
496 opp-peak-kBps = <(1267200 * 32)>;
498 opp-1401600000 {
499 opp-hz = /bits/ 64 <1401600000>;
500 opp-peak-kBps = <(1363200 * 32)>;
502 opp-1516800000 {
503 opp-hz = /bits/ 64 <1516800000>;
504 opp-peak-kBps = <(1459200 * 32)>;
506 opp-1632000000 {
507 opp-hz = /bits/ 64 <1632000000>;
508 opp-peak-kBps = <(1612800 * 32)>;
510 opp-1747200000 {
511 opp-hz = /bits/ 64 <1747200000>;
512 opp-peak-kBps = <(1689600 * 32)>;
514 opp-1862400000 {
515 opp-hz = /bits/ 64 <1862400000>;
516 opp-peak-kBps = <(1689600 * 32)>;
518 opp-1977600000 {
519 opp-hz = /bits/ 64 <1977600000>;
520 opp-peak-kBps = <(1689600 * 32)>;
522 opp-2073600000 {
523 opp-hz = /bits/ 64 <2073600000>;
524 opp-peak-kBps = <(1689600 * 32)>;
526 opp-2169600000 {
527 opp-hz = /bits/ 64 <2169600000>;
528 opp-peak-kBps = <(1689600 * 32)>;
530 opp-2284800000 {
531 opp-hz = /bits/ 64 <2284800000>;
532 opp-peak-kBps = <(1689600 * 32)>;
534 opp-2400000000 {
535 opp-hz = /bits/ 64 <2400000000>;
536 opp-peak-kBps = <(1689600 * 32)>;
538 opp-2496000000 {
539 opp-hz = /bits/ 64 <2496000000>;
540 opp-peak-kBps = <(1689600 * 32)>;
542 opp-2592000000 {
543 opp-hz = /bits/ 64 <2592000000>;
544 opp-peak-kBps = <(1689600 * 32)>;
546 opp-2688000000 {
547 opp-hz = /bits/ 64 <2688000000>;
548 opp-peak-kBps = <(1689600 * 32)>;
550 opp-2803200000 {
551 opp-hz = /bits/ 64 <2803200000>;
552 opp-peak-kBps = <(1689600 * 32)>;
554 opp-2899200000 {
555 opp-hz = /bits/ 64 <2899200000>;
556 opp-peak-kBps = <(1689600 * 32)>;
558 opp-2995200000 {
559 opp-hz = /bits/ 64 <2995200000>;
560 opp-peak-kBps = <(1689600 * 32)>;
564 qup_opp_table_100mhz: opp-table-qup100mhz {
565 compatible = "operating-points-v2";
567 opp-75000000 {
568 opp-hz = /bits/ 64 <75000000>;
569 required-opps = <&rpmhpd_opp_low_svs>;
572 opp-100000000 {
573 opp-hz = /bits/ 64 <100000000>;
574 required-opps = <&rpmhpd_opp_svs>;
579 compatible = "arm,armv8-pmuv3";
584 compatible = "arm,psci-1.0";
587 CPU_PD0: power-domain-cpu0 {
588 #power-domain-cells = <0>;
589 power-domains = <&CLUSTER_PD>;
590 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
593 CPU_PD1: power-domain-cpu1 {
594 #power-domain-cells = <0>;
595 power-domains = <&CLUSTER_PD>;
596 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
599 CPU_PD2: power-domain-cpu2 {
600 #power-domain-cells = <0>;
601 power-domains = <&CLUSTER_PD>;
602 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
605 CPU_PD3: power-domain-cpu3 {
606 #power-domain-cells = <0>;
607 power-domains = <&CLUSTER_PD>;
608 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
611 CPU_PD4: power-domain-cpu4 {
612 #power-domain-cells = <0>;
613 power-domains = <&CLUSTER_PD>;
614 domain-idle-states = <&BIG_CPU_SLEEP_0>;
617 CPU_PD5: power-domain-cpu5 {
618 #power-domain-cells = <0>;
619 power-domains = <&CLUSTER_PD>;
620 domain-idle-states = <&BIG_CPU_SLEEP_0>;
623 CPU_PD6: power-domain-cpu6 {
624 #power-domain-cells = <0>;
625 power-domains = <&CLUSTER_PD>;
626 domain-idle-states = <&BIG_CPU_SLEEP_0>;
629 CPU_PD7: power-domain-cpu7 {
630 #power-domain-cells = <0>;
631 power-domains = <&CLUSTER_PD>;
632 domain-idle-states = <&BIG_CPU_SLEEP_0>;
635 CLUSTER_PD: power-domain-cpu-cluster0 {
636 #power-domain-cells = <0>;
637 domain-idle-states = <&CLUSTER_SLEEP_0>;
641 reserved-memory {
642 #address-cells = <2>;
643 #size-cells = <2>;
646 reserved-region@80000000 {
648 no-map;
651 cmd_db: cmd-db-region@80860000 {
652 compatible = "qcom,cmd-db";
654 no-map;
657 reserved-region@80880000 {
659 no-map;
662 smem_mem: smem-region@80900000 {
665 no-map;
669 reserved-region@80b00000 {
671 no-map;
674 reserved-region@83b00000 {
676 no-map;
679 reserved-region@85b00000 {
681 no-map;
684 pil_adsp_mem: adsp-region@86c00000 {
686 no-map;
689 pil_nsp0_mem: cdsp0-region@8a100000 {
691 no-map;
694 pil_nsp1_mem: cdsp1-region@8c600000 {
696 no-map;
699 reserved-region@aeb00000 {
701 no-map;
705 smp2p-adsp {
708 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
714 qcom,local-pid = <0>;
715 qcom,remote-pid = <2>;
717 smp2p_adsp_out: master-kernel {
718 qcom,entry-name = "master-kernel";
719 #qcom,smem-state-cells = <1>;
722 smp2p_adsp_in: slave-kernel {
723 qcom,entry-name = "slave-kernel";
724 interrupt-controller;
725 #interrupt-cells = <2>;
729 smp2p-nsp0 {
732 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
738 qcom,local-pid = <0>;
739 qcom,remote-pid = <5>;
741 smp2p_nsp0_out: master-kernel {
742 qcom,entry-name = "master-kernel";
743 #qcom,smem-state-cells = <1>;
746 smp2p_nsp0_in: slave-kernel {
747 qcom,entry-name = "slave-kernel";
748 interrupt-controller;
749 #interrupt-cells = <2>;
753 smp2p-nsp1 {
756 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
762 qcom,local-pid = <0>;
763 qcom,remote-pid = <12>;
765 smp2p_nsp1_out: master-kernel {
766 qcom,entry-name = "master-kernel";
767 #qcom,smem-state-cells = <1>;
770 smp2p_nsp1_in: slave-kernel {
771 qcom,entry-name = "slave-kernel";
772 interrupt-controller;
773 #interrupt-cells = <2>;
778 compatible = "simple-bus";
779 #address-cells = <2>;
780 #size-cells = <2>;
782 dma-ranges = <0 0 0 0 0x10 0>;
785 compatible = "qcom,sc8280xp-ethqos";
788 reg-names = "stmmaceth", "rgmii";
794 clock-names = "stmmaceth",
801 interrupt-names = "macirq", "eth_lpi";
804 power-domains = <&gcc EMAC_0_GDSC>;
808 rx-fifo-depth = <4096>;
809 tx-fifo-depth = <4096>;
814 gcc: clock-controller@100000 {
815 compatible = "qcom,gcc-sc8280xp";
817 #clock-cells = <1>;
818 #reset-cells = <1>;
819 #power-domain-cells = <1>;
853 power-domains = <&rpmhpd SC8280XP_CX>;
857 compatible = "qcom,sc8280xp-ipcc", "qcom,ipcc";
860 interrupt-controller;
861 #interrupt-cells = <3>;
862 #mbox-cells = <2>;
866 compatible = "qcom,geni-se-qup";
870 clock-names = "m-ahb", "s-ahb";
873 #address-cells = <2>;
874 #size-cells = <2>;
880 compatible = "qcom,geni-i2c";
882 #address-cells = <1>;
883 #size-cells = <0>;
885 clock-names = "se";
887 power-domains = <&rpmhpd SC8280XP_CX>;
891 interconnect-names = "qup-core", "qup-config", "qup-memory";
896 compatible = "qcom,geni-spi";
898 #address-cells = <1>;
899 #size-cells = <0>;
901 clock-names = "se";
903 power-domains = <&rpmhpd SC8280XP_CX>;
907 interconnect-names = "qup-core", "qup-config", "qup-memory";
912 compatible = "qcom,geni-i2c";
914 #address-cells = <1>;
915 #size-cells = <0>;
917 clock-names = "se";
919 power-domains = <&rpmhpd SC8280XP_CX>;
923 interconnect-names = "qup-core", "qup-config", "qup-memory";
928 compatible = "qcom,geni-spi";
930 #address-cells = <1>;
931 #size-cells = <0>;
933 clock-names = "se";
935 power-domains = <&rpmhpd SC8280XP_CX>;
939 interconnect-names = "qup-core", "qup-config", "qup-memory";
944 compatible = "qcom,geni-uart";
947 clock-names = "se";
949 operating-points-v2 = <&qup_opp_table_100mhz>;
950 power-domains = <&rpmhpd SC8280XP_CX>;
953 interconnect-names = "qup-core", "qup-config";
958 compatible = "qcom,geni-i2c";
960 #address-cells = <1>;
961 #size-cells = <0>;
963 clock-names = "se";
965 power-domains = <&rpmhpd SC8280XP_CX>;
969 interconnect-names = "qup-core", "qup-config", "qup-memory";
974 compatible = "qcom,geni-spi";
976 #address-cells = <1>;
977 #size-cells = <0>;
979 clock-names = "se";
981 power-domains = <&rpmhpd SC8280XP_CX>;
985 interconnect-names = "qup-core", "qup-config", "qup-memory";
990 compatible = "qcom,geni-i2c";
992 #address-cells = <1>;
993 #size-cells = <0>;
995 clock-names = "se";
997 power-domains = <&rpmhpd SC8280XP_CX>;
1001 interconnect-names = "qup-core", "qup-config", "qup-memory";
1006 compatible = "qcom,geni-spi";
1008 #address-cells = <1>;
1009 #size-cells = <0>;
1011 clock-names = "se";
1013 power-domains = <&rpmhpd SC8280XP_CX>;
1017 interconnect-names = "qup-core", "qup-config", "qup-memory";
1022 compatible = "qcom,geni-i2c";
1024 #address-cells = <1>;
1025 #size-cells = <0>;
1027 clock-names = "se";
1029 power-domains = <&rpmhpd SC8280XP_CX>;
1033 interconnect-names = "qup-core", "qup-config", "qup-memory";
1038 compatible = "qcom,geni-spi";
1040 #address-cells = <1>;
1041 #size-cells = <0>;
1043 clock-names = "se";
1045 power-domains = <&rpmhpd SC8280XP_CX>;
1049 interconnect-names = "qup-core", "qup-config", "qup-memory";
1054 compatible = "qcom,geni-i2c";
1056 clock-names = "se";
1059 #address-cells = <1>;
1060 #size-cells = <0>;
1061 power-domains = <&rpmhpd SC8280XP_CX>;
1065 interconnect-names = "qup-core", "qup-config", "qup-memory";
1070 compatible = "qcom,geni-spi";
1072 #address-cells = <1>;
1073 #size-cells = <0>;
1075 clock-names = "se";
1077 power-domains = <&rpmhpd SC8280XP_CX>;
1081 interconnect-names = "qup-core", "qup-config", "qup-memory";
1086 compatible = "qcom,geni-i2c";
1088 #address-cells = <1>;
1089 #size-cells = <0>;
1090 clock-names = "se";
1093 power-domains = <&rpmhpd SC8280XP_CX>;
1097 interconnect-names = "qup-core", "qup-config", "qup-memory";
1102 compatible = "qcom,geni-spi";
1104 #address-cells = <1>;
1105 #size-cells = <0>;
1107 clock-names = "se";
1109 power-domains = <&rpmhpd SC8280XP_CX>;
1113 interconnect-names = "qup-core", "qup-config", "qup-memory";
1118 compatible = "qcom,geni-i2c";
1120 #address-cells = <1>;
1121 #size-cells = <0>;
1122 clock-names = "se";
1125 power-domains = <&rpmhpd SC8280XP_CX>;
1129 interconnect-names = "qup-core", "qup-config", "qup-memory";
1134 compatible = "qcom,geni-spi";
1136 #address-cells = <1>;
1137 #size-cells = <0>;
1139 clock-names = "se";
1141 power-domains = <&rpmhpd SC8280XP_CX>;
1145 interconnect-names = "qup-core", "qup-config", "qup-memory";
1151 compatible = "qcom,geni-se-qup";
1155 clock-names = "m-ahb", "s-ahb";
1158 #address-cells = <2>;
1159 #size-cells = <2>;
1165 compatible = "qcom,geni-i2c";
1167 #address-cells = <1>;
1168 #size-cells = <0>;
1169 clock-names = "se";
1172 power-domains = <&rpmhpd SC8280XP_CX>;
1176 interconnect-names = "qup-core", "qup-config", "qup-memory";
1181 compatible = "qcom,geni-spi";
1183 #address-cells = <1>;
1184 #size-cells = <0>;
1186 clock-names = "se";
1188 power-domains = <&rpmhpd SC8280XP_CX>;
1192 interconnect-names = "qup-core", "qup-config", "qup-memory";
1197 compatible = "qcom,geni-i2c";
1199 #address-cells = <1>;
1200 #size-cells = <0>;
1201 clock-names = "se";
1204 power-domains = <&rpmhpd SC8280XP_CX>;
1208 interconnect-names = "qup-core", "qup-config", "qup-memory";
1213 compatible = "qcom,geni-spi";
1215 #address-cells = <1>;
1216 #size-cells = <0>;
1218 clock-names = "se";
1220 power-domains = <&rpmhpd SC8280XP_CX>;
1224 interconnect-names = "qup-core", "qup-config", "qup-memory";
1229 compatible = "qcom,geni-i2c";
1231 #address-cells = <1>;
1232 #size-cells = <0>;
1233 clock-names = "se";
1236 power-domains = <&rpmhpd SC8280XP_CX>;
1240 interconnect-names = "qup-core", "qup-config", "qup-memory";
1245 compatible = "qcom,geni-spi";
1247 #address-cells = <1>;
1248 #size-cells = <0>;
1250 clock-names = "se";
1252 power-domains = <&rpmhpd SC8280XP_CX>;
1256 interconnect-names = "qup-core", "qup-config", "qup-memory";
1261 compatible = "qcom,geni-uart";
1264 clock-names = "se";
1266 operating-points-v2 = <&qup_opp_table_100mhz>;
1267 power-domains = <&rpmhpd SC8280XP_CX>;
1270 interconnect-names = "qup-core", "qup-config";
1275 compatible = "qcom,geni-i2c";
1277 #address-cells = <1>;
1278 #size-cells = <0>;
1279 clock-names = "se";
1282 power-domains = <&rpmhpd SC8280XP_CX>;
1286 interconnect-names = "qup-core", "qup-config", "qup-memory";
1291 compatible = "qcom,geni-spi";
1293 #address-cells = <1>;
1294 #size-cells = <0>;
1296 clock-names = "se";
1298 power-domains = <&rpmhpd SC8280XP_CX>;
1302 interconnect-names = "qup-core", "qup-config", "qup-memory";
1307 compatible = "qcom,geni-i2c";
1309 clock-names = "se";
1312 #address-cells = <1>;
1313 #size-cells = <0>;
1314 power-domains = <&rpmhpd SC8280XP_CX>;
1318 interconnect-names = "qup-core", "qup-config", "qup-memory";
1323 compatible = "qcom,geni-spi";
1325 #address-cells = <1>;
1326 #size-cells = <0>;
1328 clock-names = "se";
1330 power-domains = <&rpmhpd SC8280XP_CX>;
1334 interconnect-names = "qup-core", "qup-config", "qup-memory";
1339 compatible = "qcom,geni-i2c";
1341 #address-cells = <1>;
1342 #size-cells = <0>;
1343 clock-names = "se";
1346 power-domains = <&rpmhpd SC8280XP_CX>;
1350 interconnect-names = "qup-core", "qup-config", "qup-memory";
1355 compatible = "qcom,geni-spi";
1357 #address-cells = <1>;
1358 #size-cells = <0>;
1360 clock-names = "se";
1362 power-domains = <&rpmhpd SC8280XP_CX>;
1366 interconnect-names = "qup-core", "qup-config", "qup-memory";
1371 compatible = "qcom,geni-i2c";
1373 #address-cells = <1>;
1374 #size-cells = <0>;
1375 clock-names = "se";
1378 power-domains = <&rpmhpd SC8280XP_CX>;
1382 interconnect-names = "qup-core", "qup-config", "qup-memory";
1387 compatible = "qcom,geni-spi";
1389 #address-cells = <1>;
1390 #size-cells = <0>;
1392 clock-names = "se";
1394 power-domains = <&rpmhpd SC8280XP_CX>;
1398 interconnect-names = "qup-core", "qup-config", "qup-memory";
1403 compatible = "qcom,geni-i2c";
1405 #address-cells = <1>;
1406 #size-cells = <0>;
1407 clock-names = "se";
1410 power-domains = <&rpmhpd SC8280XP_CX>;
1414 interconnect-names = "qup-core", "qup-config", "qup-memory";
1419 compatible = "qcom,geni-spi";
1421 #address-cells = <1>;
1422 #size-cells = <0>;
1424 clock-names = "se";
1426 power-domains = <&rpmhpd SC8280XP_CX>;
1430 interconnect-names = "qup-core", "qup-config", "qup-memory";
1436 compatible = "qcom,geni-se-qup";
1440 clock-names = "m-ahb", "s-ahb";
1443 #address-cells = <2>;
1444 #size-cells = <2>;
1450 compatible = "qcom,geni-i2c";
1452 #address-cells = <1>;
1453 #size-cells = <0>;
1455 clock-names = "se";
1457 power-domains = <&rpmhpd SC8280XP_CX>;
1461 interconnect-names = "qup-core", "qup-config", "qup-memory";
1466 compatible = "qcom,geni-spi";
1468 #address-cells = <1>;
1469 #size-cells = <0>;
1471 clock-names = "se";
1473 power-domains = <&rpmhpd SC8280XP_CX>;
1477 interconnect-names = "qup-core", "qup-config", "qup-memory";
1482 compatible = "qcom,geni-i2c";
1484 #address-cells = <1>;
1485 #size-cells = <0>;
1487 clock-names = "se";
1489 power-domains = <&rpmhpd SC8280XP_CX>;
1493 interconnect-names = "qup-core", "qup-config", "qup-memory";
1498 compatible = "qcom,geni-spi";
1500 #address-cells = <1>;
1501 #size-cells = <0>;
1503 clock-names = "se";
1505 power-domains = <&rpmhpd SC8280XP_CX>;
1509 interconnect-names = "qup-core", "qup-config", "qup-memory";
1514 compatible = "qcom,geni-i2c";
1516 #address-cells = <1>;
1517 #size-cells = <0>;
1519 clock-names = "se";
1521 power-domains = <&rpmhpd SC8280XP_CX>;
1525 interconnect-names = "qup-core", "qup-config", "qup-memory";
1530 compatible = "qcom,geni-spi";
1532 #address-cells = <1>;
1533 #size-cells = <0>;
1535 clock-names = "se";
1537 power-domains = <&rpmhpd SC8280XP_CX>;
1541 interconnect-names = "qup-core", "qup-config", "qup-memory";
1546 compatible = "qcom,geni-i2c";
1548 #address-cells = <1>;
1549 #size-cells = <0>;
1551 clock-names = "se";
1553 power-domains = <&rpmhpd SC8280XP_CX>;
1557 interconnect-names = "qup-core", "qup-config", "qup-memory";
1562 compatible = "qcom,geni-spi";
1564 #address-cells = <1>;
1565 #size-cells = <0>;
1567 clock-names = "se";
1569 power-domains = <&rpmhpd SC8280XP_CX>;
1573 interconnect-names = "qup-core", "qup-config", "qup-memory";
1578 compatible = "qcom,geni-i2c";
1580 #address-cells = <1>;
1581 #size-cells = <0>;
1583 clock-names = "se";
1585 power-domains = <&rpmhpd SC8280XP_CX>;
1589 interconnect-names = "qup-core", "qup-config", "qup-memory";
1594 compatible = "qcom,geni-spi";
1596 #address-cells = <1>;
1597 #size-cells = <0>;
1599 clock-names = "se";
1601 power-domains = <&rpmhpd SC8280XP_CX>;
1605 interconnect-names = "qup-core", "qup-config", "qup-memory";
1610 compatible = "qcom,geni-i2c";
1612 #address-cells = <1>;
1613 #size-cells = <0>;
1615 clock-names = "se";
1617 power-domains = <&rpmhpd SC8280XP_CX>;
1621 interconnect-names = "qup-core", "qup-config", "qup-memory";
1626 compatible = "qcom,geni-spi";
1628 #address-cells = <1>;
1629 #size-cells = <0>;
1631 clock-names = "se";
1633 power-domains = <&rpmhpd SC8280XP_CX>;
1637 interconnect-names = "qup-core", "qup-config", "qup-memory";
1642 compatible = "qcom,geni-i2c";
1644 #address-cells = <1>;
1645 #size-cells = <0>;
1647 clock-names = "se";
1649 power-domains = <&rpmhpd SC8280XP_CX>;
1653 interconnect-names = "qup-core", "qup-config", "qup-memory";
1658 compatible = "qcom,geni-spi";
1660 #address-cells = <1>;
1661 #size-cells = <0>;
1663 clock-names = "se";
1665 power-domains = <&rpmhpd SC8280XP_CX>;
1669 interconnect-names = "qup-core", "qup-config", "qup-memory";
1674 compatible = "qcom,geni-i2c";
1676 #address-cells = <1>;
1677 #size-cells = <0>;
1679 clock-names = "se";
1681 power-domains = <&rpmhpd SC8280XP_CX>;
1685 interconnect-names = "qup-core", "qup-config", "qup-memory";
1690 compatible = "qcom,geni-spi";
1692 #address-cells = <1>;
1693 #size-cells = <0>;
1695 clock-names = "se";
1697 power-domains = <&rpmhpd SC8280XP_CX>;
1701 interconnect-names = "qup-core", "qup-config", "qup-memory";
1707 compatible = "qcom,prng-ee";
1710 clock-names = "core";
1715 compatible = "qcom,pcie-sc8280xp";
1722 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1723 #address-cells = <3>;
1724 #size-cells = <2>;
1727 bus-range = <0x00 0xff>;
1729 dma-coherent;
1731 linux,pci-domain = <6>;
1732 num-lanes = <1>;
1738 interrupt-names = "msi0", "msi1", "msi2", "msi3";
1740 #interrupt-cells = <1>;
1741 interrupt-map-mask = <0 0 0 0x7>;
1742 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1756 clock-names = "aux",
1766 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>;
1767 assigned-clock-rates = <19200000>;
1771 interconnect-names = "pcie-mem", "cpu-pcie";
1774 reset-names = "pci";
1776 power-domains = <&gcc PCIE_4_GDSC>;
1779 phy-names = "pciephy";
1785 compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy";
1794 clock-names = "aux", "cfg_ahb", "ref", "rchng",
1797 assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>;
1798 assigned-clock-rates = <100000000>;
1800 power-domains = <&gcc PCIE_4_GDSC>;
1803 reset-names = "phy";
1805 #clock-cells = <0>;
1806 clock-output-names = "pcie_4_pipe_clk";
1808 #phy-cells = <0>;
1815 compatible = "qcom,pcie-sc8280xp";
1822 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1823 #address-cells = <3>;
1824 #size-cells = <2>;
1827 bus-range = <0x00 0xff>;
1829 dma-coherent;
1831 linux,pci-domain = <5>;
1832 num-lanes = <2>;
1838 interrupt-names = "msi0", "msi1", "msi2", "msi3";
1840 #interrupt-cells = <1>;
1841 interrupt-map-mask = <0 0 0 0x7>;
1842 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>,
1855 clock-names = "aux",
1864 assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>;
1865 assigned-clock-rates = <19200000>;
1869 interconnect-names = "pcie-mem", "cpu-pcie";
1872 reset-names = "pci";
1874 power-domains = <&gcc PCIE_3B_GDSC>;
1877 phy-names = "pciephy";
1883 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
1892 clock-names = "aux", "cfg_ahb", "ref", "rchng",
1895 assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>;
1896 assigned-clock-rates = <100000000>;
1898 power-domains = <&gcc PCIE_3B_GDSC>;
1901 reset-names = "phy";
1903 #clock-cells = <0>;
1904 clock-output-names = "pcie_3b_pipe_clk";
1906 #phy-cells = <0>;
1913 compatible = "qcom,pcie-sc8280xp";
1920 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1921 #address-cells = <3>;
1922 #size-cells = <2>;
1925 bus-range = <0x00 0xff>;
1927 dma-coherent;
1929 linux,pci-domain = <4>;
1930 num-lanes = <4>;
1936 interrupt-names = "msi0", "msi1", "msi2", "msi3";
1938 #interrupt-cells = <1>;
1939 interrupt-map-mask = <0 0 0 0x7>;
1940 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
1953 clock-names = "aux",
1962 assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>;
1963 assigned-clock-rates = <19200000>;
1967 interconnect-names = "pcie-mem", "cpu-pcie";
1970 reset-names = "pci";
1972 power-domains = <&gcc PCIE_3A_GDSC>;
1975 phy-names = "pciephy";
1981 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
1991 clock-names = "aux", "cfg_ahb", "ref", "rchng",
1994 assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>;
1995 assigned-clock-rates = <100000000>;
1997 power-domains = <&gcc PCIE_3A_GDSC>;
2000 reset-names = "phy";
2002 qcom,4ln-config-sel = <&tcsr 0xa044 1>;
2004 #clock-cells = <0>;
2005 clock-output-names = "pcie_3a_pipe_clk";
2007 #phy-cells = <0>;
2014 compatible = "qcom,pcie-sc8280xp";
2021 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2022 #address-cells = <3>;
2023 #size-cells = <2>;
2026 bus-range = <0x00 0xff>;
2028 dma-coherent;
2030 linux,pci-domain = <3>;
2031 num-lanes = <2>;
2037 interrupt-names = "msi0", "msi1", "msi2", "msi3";
2039 #interrupt-cells = <1>;
2040 interrupt-map-mask = <0 0 0 0x7>;
2041 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
2054 clock-names = "aux",
2063 assigned-clocks = <&gcc GCC_PCIE_2B_AUX_CLK>;
2064 assigned-clock-rates = <19200000>;
2068 interconnect-names = "pcie-mem", "cpu-pcie";
2071 reset-names = "pci";
2073 power-domains = <&gcc PCIE_2B_GDSC>;
2076 phy-names = "pciephy";
2082 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
2091 clock-names = "aux", "cfg_ahb", "ref", "rchng",
2094 assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>;
2095 assigned-clock-rates = <100000000>;
2097 power-domains = <&gcc PCIE_2B_GDSC>;
2100 reset-names = "phy";
2102 #clock-cells = <0>;
2103 clock-output-names = "pcie_2b_pipe_clk";
2105 #phy-cells = <0>;
2112 compatible = "qcom,pcie-sc8280xp";
2119 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2120 #address-cells = <3>;
2121 #size-cells = <2>;
2124 bus-range = <0x00 0xff>;
2126 dma-coherent;
2128 linux,pci-domain = <2>;
2129 num-lanes = <4>;
2135 interrupt-names = "msi0", "msi1", "msi2", "msi3";
2137 #interrupt-cells = <1>;
2138 interrupt-map-mask = <0 0 0 0x7>;
2139 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
2152 clock-names = "aux",
2161 assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>;
2162 assigned-clock-rates = <19200000>;
2166 interconnect-names = "pcie-mem", "cpu-pcie";
2169 reset-names = "pci";
2171 power-domains = <&gcc PCIE_2A_GDSC>;
2174 phy-names = "pciephy";
2180 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
2190 clock-names = "aux", "cfg_ahb", "ref", "rchng",
2193 assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>;
2194 assigned-clock-rates = <100000000>;
2196 power-domains = <&gcc PCIE_2A_GDSC>;
2199 reset-names = "phy";
2201 qcom,4ln-config-sel = <&tcsr 0xa044 0>;
2203 #clock-cells = <0>;
2204 clock-output-names = "pcie_2a_pipe_clk";
2206 #phy-cells = <0>;
2212 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
2213 "jedec,ufs-2.0";
2217 phy-names = "ufsphy";
2218 lanes-per-direction = <2>;
2219 #reset-cells = <1>;
2221 reset-names = "rst";
2223 power-domains = <&gcc UFS_PHY_GDSC>;
2224 required-opps = <&rpmhpd_opp_nom>;
2227 dma-coherent;
2237 clock-names = "core_clk",
2245 freq-table-hz = <75000000 300000000>,
2257 compatible = "qcom,sc8280xp-qmp-ufs-phy";
2262 clock-names = "ref", "ref_aux";
2264 power-domains = <&gcc UFS_PHY_GDSC>;
2267 reset-names = "ufsphy";
2269 #phy-cells = <0>;
2275 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
2276 "jedec,ufs-2.0";
2280 phy-names = "ufsphy";
2281 lanes-per-direction = <2>;
2282 #reset-cells = <1>;
2284 reset-names = "rst";
2286 power-domains = <&gcc UFS_CARD_GDSC>;
2289 dma-coherent;
2299 clock-names = "core_clk",
2307 freq-table-hz = <75000000 300000000>,
2319 compatible = "qcom,sc8280xp-qmp-ufs-phy";
2324 clock-names = "ref", "ref_aux";
2326 power-domains = <&gcc UFS_CARD_GDSC>;
2329 reset-names = "ufsphy";
2331 #phy-cells = <0>;
2337 compatible = "qcom,tcsr-mutex";
2339 #hwlock-cells = <1>;
2343 compatible = "qcom,sc8280xp-tcsr", "syscon";
2348 compatible = "qcom,adreno-690.0", "qcom,adreno";
2353 reg-names = "kgsl_3d0_reg_memory",
2358 operating-points-v2 = <&gpu_opp_table>;
2362 interconnect-names = "gfx-mem";
2363 #cooling-cells = <2>;
2367 gpu_opp_table: opp-table {
2368 compatible = "operating-points-v2";
2370 opp-270000000 {
2371 opp-hz = /bits/ 64 <270000000>;
2372 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2373 opp-peak-kBps = <451000>;
2376 opp-410000000 {
2377 opp-hz = /bits/ 64 <410000000>;
2378 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2379 opp-peak-kBps = <1555000>;
2382 opp-500000000 {
2383 opp-hz = /bits/ 64 <500000000>;
2384 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2385 opp-peak-kBps = <1555000>;
2388 opp-547000000 {
2389 opp-hz = /bits/ 64 <547000000>;
2390 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2391 opp-peak-kBps = <1555000>;
2394 opp-606000000 {
2395 opp-hz = /bits/ 64 <606000000>;
2396 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2397 opp-peak-kBps = <2736000>;
2400 opp-640000000 {
2401 opp-hz = /bits/ 64 <640000000>;
2402 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2403 opp-peak-kBps = <2736000>;
2406 opp-655000000 {
2407 opp-hz = /bits/ 64 <655000000>;
2408 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2409 opp-peak-kBps = <2736000>;
2412 opp-690000000 {
2413 opp-hz = /bits/ 64 <690000000>;
2414 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2415 opp-peak-kBps = <2736000>;
2421 compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu";
2425 reg-names = "gmu", "rscc", "gmu_pdc";
2428 interrupt-names = "hfi", "gmu";
2436 clock-names = "gmu",
2443 power-domains = <&gpucc GPU_CC_CX_GDSC>,
2445 power-domain-names = "cx",
2448 operating-points-v2 = <&gmu_opp_table>;
2450 gmu_opp_table: opp-table {
2451 compatible = "operating-points-v2";
2453 opp-200000000 {
2454 opp-hz = /bits/ 64 <200000000>;
2455 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2458 opp-500000000 {
2459 opp-hz = /bits/ 64 <500000000>;
2460 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2465 gpucc: clock-controller@3d90000 {
2466 compatible = "qcom,sc8280xp-gpucc";
2471 clock-names = "bi_tcxo",
2475 power-domains = <&rpmhpd SC8280XP_GFX>;
2476 #clock-cells = <1>;
2477 #reset-cells = <1>;
2478 #power-domain-cells = <1>;
2482 compatible = "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu",
2483 "qcom,smmu-500", "arm,mmu-500";
2485 #iommu-cells = <2>;
2486 #global-interrupts = <2>;
2509 clock-names = "gcc_gpu_memnoc_gfx_clk",
2517 power-domains = <&gpucc GPU_CC_CX_GDSC>;
2518 dma-coherent;
2522 compatible = "qcom,sc8280xp-usb-hs-phy",
2523 "qcom,usb-snps-hs-5nm-phy";
2526 clock-names = "ref";
2529 #phy-cells = <0>;
2535 compatible = "qcom,sc8280xp-usb-hs-phy",
2536 "qcom,usb-snps-hs-5nm-phy";
2539 clock-names = "ref";
2542 #phy-cells = <0>;
2548 compatible = "qcom,sc8280xp-usb-hs-phy",
2549 "qcom,usb-snps-hs-5nm-phy";
2552 clock-names = "ref";
2555 #phy-cells = <0>;
2561 compatible = "qcom,sc8280xp-usb-hs-phy",
2562 "qcom,usb-snps-hs-5nm-phy";
2565 clock-names = "ref";
2568 #phy-cells = <0>;
2574 compatible = "qcom,sc8280xp-usb-hs-phy",
2575 "qcom,usb-snps-hs-5nm-phy";
2578 clock-names = "ref";
2581 #phy-cells = <0>;
2587 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
2594 clock-names = "aux", "ref", "com_aux", "pipe";
2598 reset-names = "phy", "phy_phy";
2600 power-domains = <&gcc USB30_MP_GDSC>;
2602 #clock-cells = <0>;
2603 clock-output-names = "usb2_phy0_pipe_clk";
2605 #phy-cells = <0>;
2611 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
2618 clock-names = "aux", "ref", "com_aux", "pipe";
2622 reset-names = "phy", "phy_phy";
2624 power-domains = <&gcc USB30_MP_GDSC>;
2626 #clock-cells = <0>;
2627 clock-output-names = "usb2_phy1_pipe_clk";
2629 #phy-cells = <0>;
2635 compatible = "qcom,sc8280xp-adsp-pas";
2638 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
2644 interrupt-names = "wdog", "fatal", "ready",
2645 "handover", "stop-ack", "shutdown-ack";
2648 clock-names = "xo";
2650 power-domains = <&rpmhpd SC8280XP_LCX>,
2652 power-domain-names = "lcx", "lmx";
2654 memory-region = <&pil_adsp_mem>;
2658 qcom,smem-states = <&smp2p_adsp_out 0>;
2659 qcom,smem-state-names = "stop";
2663 remoteproc_adsp_glink: glink-edge {
2664 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2671 qcom,remote-pid = <2>;
2675 qcom,glink-channels = "adsp_apps";
2678 #address-cells = <1>;
2679 #size-cells = <0>;
2684 #sound-dai-cells = <0>;
2685 qcom,protection-domain = "avs/audio",
2688 compatible = "qcom,q6apm-dais";
2693 compatible = "qcom,q6apm-lpass-dais";
2694 #sound-dai-cells = <1>;
2701 qcom,protection-domain = "avs/audio",
2703 q6prmcc: clock-controller {
2704 compatible = "qcom,q6prm-lpass-clocks";
2705 #clock-cells = <2>;
2713 compatible = "qcom,sc8280xp-lpass-rx-macro";
2720 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2721 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2723 assigned-clock-rates = <19200000>, <19200000>;
2725 clock-output-names = "mclk";
2726 #clock-cells = <0>;
2727 #sound-dai-cells = <1>;
2729 pinctrl-names = "default";
2730 pinctrl-0 = <&rx_swr_default>;
2736 compatible = "qcom,soundwire-v1.6.0";
2740 clock-names = "iface";
2742 reset-names = "swr_audio_cgcr";
2745 qcom,din-ports = <0>;
2746 qcom,dout-ports = <5>;
2748 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2749 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>;
2750 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>;
2751 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff>;
2752 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff>;
2753 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2754 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff>;
2755 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2756 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2758 #sound-dai-cells = <1>;
2759 #address-cells = <2>;
2760 #size-cells = <0>;
2766 compatible = "qcom,sc8280xp-lpass-tx-macro";
2768 pinctrl-names = "default";
2769 pinctrl-0 = <&tx_swr_default>;
2776 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2777 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2779 assigned-clock-rates = <19200000>, <19200000>;
2780 clock-output-names = "mclk";
2782 #clock-cells = <0>;
2783 #sound-dai-cells = <1>;
2789 compatible = "qcom,sc8280xp-lpass-wsa-macro";
2796 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2797 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2799 assigned-clock-rates = <19200000>, <19200000>;
2801 #clock-cells = <0>;
2802 clock-output-names = "mclk";
2803 #sound-dai-cells = <1>;
2805 pinctrl-names = "default";
2806 pinctrl-0 = <&wsa_swr_default>;
2813 compatible = "qcom,soundwire-v1.6.0";
2816 clock-names = "iface";
2818 reset-names = "swr_audio_cgcr";
2821 qcom,din-ports = <2>;
2822 qcom,dout-ports = <6>;
2824 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2825 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2826 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2827 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2828 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2829 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2830 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2831 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2832 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2834 #sound-dai-cells = <1>;
2835 #address-cells = <2>;
2836 #size-cells = <0>;
2841 lpass_audiocc: clock-controller@32a9000 {
2842 compatible = "qcom,sc8280xp-lpassaudiocc";
2844 #clock-cells = <1>;
2845 #reset-cells = <1>;
2849 compatible = "qcom,soundwire-v1.6.0";
2853 interrupt-names = "core", "wakeup";
2856 clock-names = "iface";
2858 reset-names = "swr_audio_cgcr";
2860 #sound-dai-cells = <1>;
2861 #address-cells = <2>;
2862 #size-cells = <0>;
2864 qcom,din-ports = <4>;
2865 qcom,dout-ports = <0>;
2866 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2867 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02 0x00>;
2868 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2869 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2870 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2871 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2872 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2873 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2874 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00 0x01>;
2880 compatible = "qcom,sc8280xp-lpass-va-macro";
2886 clock-names = "mclk", "macro", "dcodec", "npl";
2887 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2888 assigned-clock-rates = <19200000>;
2890 #clock-cells = <0>;
2891 clock-output-names = "fsgen";
2892 #sound-dai-cells = <1>;
2898 compatible = "qcom,sc8280xp-lpass-lpi-pinctrl";
2901 gpio-controller;
2902 #gpio-cells = <2>;
2903 gpio-ranges = <&lpass_tlmm 0 0 19>;
2907 clock-names = "core", "audio";
2911 tx_swr_default: tx-swr-default-state {
2912 clk-pins {
2915 drive-strength = <2>;
2916 slew-rate = <1>;
2917 bias-disable;
2920 data-pins {
2923 drive-strength = <2>;
2924 slew-rate = <1>;
2925 bias-bus-hold;
2929 rx_swr_default: rx-swr-default-state {
2930 clk-pins {
2933 drive-strength = <2>;
2934 slew-rate = <1>;
2935 bias-disable;
2938 data-pins {
2941 drive-strength = <2>;
2942 slew-rate = <1>;
2943 bias-bus-hold;
2947 dmic01_default: dmic01-default-state {
2948 clk-pins {
2951 drive-strength = <8>;
2952 output-high;
2955 data-pins {
2958 drive-strength = <8>;
2959 input-enable;
2963 dmic01_sleep: dmic01-sleep-state {
2964 clk-pins {
2967 drive-strength = <2>;
2968 bias-disable;
2969 output-low;
2972 data-pins {
2975 drive-strength = <2>;
2976 bias-pull-down;
2977 input-enable;
2981 dmic02_default: dmic02-default-state {
2982 clk-pins {
2985 drive-strength = <8>;
2986 output-high;
2989 data-pins {
2992 drive-strength = <8>;
2993 input-enable;
2997 dmic02_sleep: dmic02-sleep-state {
2998 clk-pins {
3001 drive-strength = <2>;
3002 bias-disable;
3003 output-low;
3006 data-pins {
3009 drive-strength = <2>;
3010 bias-pull-down;
3011 input-enable;
3015 wsa_swr_default: wsa-swr-default-state {
3016 clk-pins {
3019 drive-strength = <2>;
3020 slew-rate = <1>;
3021 bias-disable;
3024 data-pins {
3027 drive-strength = <2>;
3028 slew-rate = <1>;
3029 bias-bus-hold;
3033 wsa2_swr_default: wsa2-swr-default-state {
3034 clk-pins {
3037 drive-strength = <2>;
3038 slew-rate = <1>;
3039 bias-disable;
3042 data-pins {
3045 drive-strength = <2>;
3046 slew-rate = <1>;
3047 bias-bus-hold;
3052 lpasscc: clock-controller@33e0000 {
3053 compatible = "qcom,sc8280xp-lpasscc";
3055 #clock-cells = <1>;
3056 #reset-cells = <1>;
3060 compatible = "qcom,sc8280xp-sdhci", "qcom,sdhci-msm-v5";
3065 interrupt-names = "hc_irq", "pwr_irq";
3070 clock-names = "iface", "core", "xo";
3074 interconnect-names = "sdhc-ddr","cpu-sdhc";
3076 power-domains = <&rpmhpd SC8280XP_CX>;
3077 operating-points-v2 = <&sdc2_opp_table>;
3078 bus-width = <4>;
3079 dma-coherent;
3083 sdc2_opp_table: opp-table {
3084 compatible = "operating-points-v2";
3086 opp-100000000 {
3087 opp-hz = /bits/ 64 <100000000>;
3088 required-opps = <&rpmhpd_opp_low_svs>;
3089 opp-peak-kBps = <1800000 400000>;
3090 opp-avg-kBps = <100000 0>;
3093 opp-202000000 {
3094 opp-hz = /bits/ 64 <202000000>;
3095 required-opps = <&rpmhpd_opp_svs_l1>;
3096 opp-peak-kBps = <5400000 1600000>;
3097 opp-avg-kBps = <200000 0>;
3103 compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
3110 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
3112 power-domains = <&gcc USB30_PRIM_GDSC>;
3116 reset-names = "phy", "common";
3118 #clock-cells = <1>;
3119 #phy-cells = <1>;
3124 #address-cells = <1>;
3125 #size-cells = <0>;
3142 compatible = "qcom,sc8280xp-usb-hs-phy",
3143 "qcom,usb-snps-hs-5nm-phy";
3145 #phy-cells = <0>;
3148 clock-names = "ref";
3156 compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
3163 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
3165 power-domains = <&gcc USB30_SEC_GDSC>;
3169 reset-names = "phy", "common";
3171 #clock-cells = <1>;
3172 #phy-cells = <1>;
3177 #address-cells = <1>;
3178 #size-cells = <0>;
3195 compatible = "qcom,sc8280xp-dp-phy";
3203 clock-names = "aux", "cfg_ahb";
3204 power-domains = <&rpmhpd SC8280XP_MX>;
3206 #clock-cells = <1>;
3207 #phy-cells = <0>;
3213 compatible = "qcom,sc8280xp-dp-phy";
3221 clock-names = "aux", "cfg_ahb";
3222 power-domains = <&rpmhpd SC8280XP_MX>;
3224 #clock-cells = <1>;
3225 #phy-cells = <0>;
3231 compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
3238 operating-points-v2 = <&llcc_bwmon_opp_table>;
3240 llcc_bwmon_opp_table: opp-table {
3241 compatible = "operating-points-v2";
3243 opp-0 {
3244 opp-peak-kBps = <762000>;
3246 opp-1 {
3247 opp-peak-kBps = <1720000>;
3249 opp-2 {
3250 opp-peak-kBps = <2086000>;
3252 opp-3 {
3253 opp-peak-kBps = <2597000>;
3255 opp-4 {
3256 opp-peak-kBps = <2929000>;
3258 opp-5 {
3259 opp-peak-kBps = <3879000>;
3261 opp-6 {
3262 opp-peak-kBps = <5161000>;
3264 opp-7 {
3265 opp-peak-kBps = <5931000>;
3267 opp-8 {
3268 opp-peak-kBps = <6515000>;
3270 opp-9 {
3271 opp-peak-kBps = <7980000>;
3273 opp-10 {
3274 opp-peak-kBps = <8136000>;
3276 opp-11 {
3277 opp-peak-kBps = <10437000>;
3279 opp-12 {
3280 opp-peak-kBps = <12191000>;
3286 compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,sdm845-bwmon";
3292 operating-points-v2 = <&cpu_bwmon_opp_table>;
3294 cpu_bwmon_opp_table: opp-table {
3295 compatible = "operating-points-v2";
3297 opp-0 {
3298 opp-peak-kBps = <2288000>;
3300 opp-1 {
3301 opp-peak-kBps = <4577000>;
3303 opp-2 {
3304 opp-peak-kBps = <7110000>;
3306 opp-3 {
3307 opp-peak-kBps = <9155000>;
3309 opp-4 {
3310 opp-peak-kBps = <12298000>;
3312 opp-5 {
3313 opp-peak-kBps = <14236000>;
3315 opp-6 {
3316 opp-peak-kBps = <15258001>;
3321 system-cache-controller@9200000 {
3322 compatible = "qcom,sc8280xp-llcc";
3328 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
3335 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
3337 #address-cells = <2>;
3338 #size-cells = <2>;
3350 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
3353 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3355 assigned-clock-rates = <19200000>, <200000000>;
3357 interrupts-extended = <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
3361 interrupt-names = "pwr_event",
3366 power-domains = <&gcc USB30_PRIM_GDSC>;
3367 required-opps = <&rpmhpd_opp_nom>;
3373 interconnect-names = "usb-ddr", "apps-usb";
3375 wakeup-source;
3385 phy-names = "usb2-phy", "usb3-phy";
3395 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
3397 #address-cells = <2>;
3398 #size-cells = <2>;
3410 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
3413 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3415 assigned-clock-rates = <19200000>, <200000000>;
3417 interrupts-extended = <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
3421 interrupt-names = "pwr_event",
3426 power-domains = <&gcc USB30_SEC_GDSC>;
3427 required-opps = <&rpmhpd_opp_nom>;
3433 interconnect-names = "usb-ddr", "apps-usb";
3435 wakeup-source;
3445 phy-names = "usb2-phy", "usb3-phy";
3454 camcc: clock-controller@ad00000 {
3455 compatible = "qcom,sc8280xp-camcc";
3461 power-domains = <&rpmhpd SC8280XP_MMCX>;
3462 required-opps = <&rpmhpd_opp_low_svs>;
3463 #clock-cells = <1>;
3464 #reset-cells = <1>;
3465 #power-domain-cells = <1>;
3468 mdss0: display-subsystem@ae00000 {
3469 compatible = "qcom,sc8280xp-mdss";
3471 reg-names = "mdss";
3476 clock-names = "iface",
3482 interconnect-names = "mdp0-mem", "mdp1-mem";
3484 power-domains = <&dispcc0 MDSS_GDSC>;
3487 interrupt-controller;
3488 #interrupt-cells = <1>;
3489 #address-cells = <2>;
3490 #size-cells = <2>;
3495 mdss0_mdp: display-controller@ae01000 {
3496 compatible = "qcom,sc8280xp-dpu";
3499 reg-names = "mdp", "vbif";
3507 clock-names = "bus",
3513 interrupt-parent = <&mdss0>;
3515 power-domains = <&rpmhpd SC8280XP_MMCX>;
3517 assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
3518 assigned-clock-rates = <19200000>;
3519 operating-points-v2 = <&mdss0_mdp_opp_table>;
3522 #address-cells = <1>;
3523 #size-cells = <0>;
3528 remote-endpoint = <&mdss0_dp0_in>;
3535 remote-endpoint = <&mdss0_dp1_in>;
3542 remote-endpoint = <&mdss0_dp3_in>;
3549 remote-endpoint = <&mdss0_dp2_in>;
3554 mdss0_mdp_opp_table: opp-table {
3555 compatible = "operating-points-v2";
3557 opp-200000000 {
3558 opp-hz = /bits/ 64 <200000000>;
3559 required-opps = <&rpmhpd_opp_low_svs>;
3562 opp-300000000 {
3563 opp-hz = /bits/ 64 <300000000>;
3564 required-opps = <&rpmhpd_opp_svs>;
3567 opp-375000000 {
3568 opp-hz = /bits/ 64 <375000000>;
3569 required-opps = <&rpmhpd_opp_svs_l1>;
3572 opp-500000000 {
3573 opp-hz = /bits/ 64 <500000000>;
3574 required-opps = <&rpmhpd_opp_nom>;
3576 opp-600000000 {
3577 opp-hz = /bits/ 64 <600000000>;
3578 required-opps = <&rpmhpd_opp_turbo_l1>;
3583 mdss0_dp0: displayport-controller@ae90000 {
3584 compatible = "qcom,sc8280xp-dp";
3590 interrupt-parent = <&mdss0>;
3597 clock-names = "core_iface", "core_aux",
3602 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
3604 assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3608 phy-names = "dp";
3610 #sound-dai-cells = <0>;
3612 operating-points-v2 = <&mdss0_dp0_opp_table>;
3613 power-domains = <&rpmhpd SC8280XP_MMCX>;
3618 #address-cells = <1>;
3619 #size-cells = <0>;
3625 remote-endpoint = <&mdss0_intf0_out>;
3637 mdss0_dp0_opp_table: opp-table {
3638 compatible = "operating-points-v2";
3640 opp-160000000 {
3641 opp-hz = /bits/ 64 <160000000>;
3642 required-opps = <&rpmhpd_opp_low_svs>;
3645 opp-270000000 {
3646 opp-hz = /bits/ 64 <270000000>;
3647 required-opps = <&rpmhpd_opp_svs>;
3650 opp-540000000 {
3651 opp-hz = /bits/ 64 <540000000>;
3652 required-opps = <&rpmhpd_opp_svs_l1>;
3655 opp-810000000 {
3656 opp-hz = /bits/ 64 <810000000>;
3657 required-opps = <&rpmhpd_opp_nom>;
3662 mdss0_dp1: displayport-controller@ae98000 {
3663 compatible = "qcom,sc8280xp-dp";
3669 interrupt-parent = <&mdss0>;
3676 clock-names = "core_iface", "core_aux",
3680 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
3682 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3686 phy-names = "dp";
3688 #sound-dai-cells = <0>;
3690 operating-points-v2 = <&mdss0_dp1_opp_table>;
3691 power-domains = <&rpmhpd SC8280XP_MMCX>;
3696 #address-cells = <1>;
3697 #size-cells = <0>;
3703 remote-endpoint = <&mdss0_intf4_out>;
3715 mdss0_dp1_opp_table: opp-table {
3716 compatible = "operating-points-v2";
3718 opp-160000000 {
3719 opp-hz = /bits/ 64 <160000000>;
3720 required-opps = <&rpmhpd_opp_low_svs>;
3723 opp-270000000 {
3724 opp-hz = /bits/ 64 <270000000>;
3725 required-opps = <&rpmhpd_opp_svs>;
3728 opp-540000000 {
3729 opp-hz = /bits/ 64 <540000000>;
3730 required-opps = <&rpmhpd_opp_svs_l1>;
3733 opp-810000000 {
3734 opp-hz = /bits/ 64 <810000000>;
3735 required-opps = <&rpmhpd_opp_nom>;
3740 mdss0_dp2: displayport-controller@ae9a000 {
3741 compatible = "qcom,sc8280xp-dp";
3753 clock-names = "core_iface", "core_aux",
3756 interrupt-parent = <&mdss0>;
3759 phy-names = "dp";
3760 power-domains = <&rpmhpd SC8280XP_MMCX>;
3762 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
3764 assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>;
3765 operating-points-v2 = <&mdss0_dp2_opp_table>;
3767 #sound-dai-cells = <0>;
3772 #address-cells = <1>;
3773 #size-cells = <0>;
3778 remote-endpoint = <&mdss0_intf6_out>;
3787 mdss0_dp2_opp_table: opp-table {
3788 compatible = "operating-points-v2";
3790 opp-160000000 {
3791 opp-hz = /bits/ 64 <160000000>;
3792 required-opps = <&rpmhpd_opp_low_svs>;
3795 opp-270000000 {
3796 opp-hz = /bits/ 64 <270000000>;
3797 required-opps = <&rpmhpd_opp_svs>;
3800 opp-540000000 {
3801 opp-hz = /bits/ 64 <540000000>;
3802 required-opps = <&rpmhpd_opp_svs_l1>;
3805 opp-810000000 {
3806 opp-hz = /bits/ 64 <810000000>;
3807 required-opps = <&rpmhpd_opp_nom>;
3812 mdss0_dp3: displayport-controller@aea0000 {
3813 compatible = "qcom,sc8280xp-dp";
3825 clock-names = "core_iface", "core_aux",
3828 interrupt-parent = <&mdss0>;
3831 phy-names = "dp";
3832 power-domains = <&rpmhpd SC8280XP_MMCX>;
3834 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
3836 assigned-clock-parents = <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>;
3837 operating-points-v2 = <&mdss0_dp3_opp_table>;
3839 #sound-dai-cells = <0>;
3844 #address-cells = <1>;
3845 #size-cells = <0>;
3850 remote-endpoint = <&mdss0_intf5_out>;
3859 mdss0_dp3_opp_table: opp-table {
3860 compatible = "operating-points-v2";
3862 opp-160000000 {
3863 opp-hz = /bits/ 64 <160000000>;
3864 required-opps = <&rpmhpd_opp_low_svs>;
3867 opp-270000000 {
3868 opp-hz = /bits/ 64 <270000000>;
3869 required-opps = <&rpmhpd_opp_svs>;
3872 opp-540000000 {
3873 opp-hz = /bits/ 64 <540000000>;
3874 required-opps = <&rpmhpd_opp_svs_l1>;
3877 opp-810000000 {
3878 opp-hz = /bits/ 64 <810000000>;
3879 required-opps = <&rpmhpd_opp_nom>;
3886 compatible = "qcom,sc8280xp-dp-phy";
3894 clock-names = "aux", "cfg_ahb";
3895 power-domains = <&rpmhpd SC8280XP_MX>;
3897 #clock-cells = <1>;
3898 #phy-cells = <0>;
3904 compatible = "qcom,sc8280xp-dp-phy";
3912 clock-names = "aux", "cfg_ahb";
3913 power-domains = <&rpmhpd SC8280XP_MX>;
3915 #clock-cells = <1>;
3916 #phy-cells = <0>;
3921 dispcc0: clock-controller@af00000 {
3922 compatible = "qcom,sc8280xp-dispcc0";
3940 power-domains = <&rpmhpd SC8280XP_MMCX>;
3942 #clock-cells = <1>;
3943 #power-domain-cells = <1>;
3944 #reset-cells = <1>;
3949 pdc: interrupt-controller@b220000 {
3950 compatible = "qcom,sc8280xp-pdc", "qcom,pdc";
3952 qcom,pdc-ranges = <0 480 40>,
4009 #interrupt-cells = <2>;
4010 interrupt-parent = <&intc>;
4011 interrupt-controller;
4014 tsens0: thermal-sensor@c263000 {
4015 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
4019 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
4021 interrupt-names = "uplow", "critical";
4022 #thermal-sensor-cells = <1>;
4025 tsens1: thermal-sensor@c265000 {
4026 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
4030 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
4032 interrupt-names = "uplow", "critical";
4033 #thermal-sensor-cells = <1>;
4036 aoss_qmp: power-management@c300000 {
4037 compatible = "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp";
4039 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>;
4042 #clock-cells = <0>;
4046 compatible = "qcom,rpmh-stats";
4052 compatible = "qcom,spmi-pmic-arb";
4058 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4059 interrupt-names = "periph_irq";
4060 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
4063 #address-cells = <2>;
4064 #size-cells = <0>;
4065 interrupt-controller;
4066 #interrupt-cells = <4>;
4070 compatible = "qcom,sc8280xp-tlmm";
4073 gpio-controller;
4074 #gpio-cells = <2>;
4075 interrupt-controller;
4076 #interrupt-cells = <2>;
4077 gpio-ranges = <&tlmm 0 0 230>;
4078 wakeup-parent = <&pdc>;
4082 compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500";
4084 #iommu-cells = <2>;
4085 #global-interrupts = <2>;
4218 intc: interrupt-controller@17a00000 {
4219 compatible = "arm,gic-v3";
4220 interrupt-controller;
4221 #interrupt-cells = <3>;
4225 #redistributor-regions = <1>;
4226 redistributor-stride = <0 0x20000>;
4228 #address-cells = <2>;
4229 #size-cells = <2>;
4232 msi-controller@17a40000 {
4233 compatible = "arm,gic-v3-its";
4235 msi-controller;
4236 #msi-cells = <1>;
4241 compatible = "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt";
4248 compatible = "arm,armv7-timer-mem";
4250 #address-cells = <1>;
4251 #size-cells = <1>;
4255 frame-number = <0>;
4263 frame-number = <1>;
4270 frame-number = <2>;
4277 frame-number = <3>;
4284 frame-number = <4>;
4291 frame-number = <5>;
4298 frame-number = <6>;
4306 compatible = "qcom,rpmh-rsc";
4310 reg-names = "drv-0", "drv-1", "drv-2";
4314 qcom,tcs-offset = <0xd00>;
4315 qcom,drv-id = <2>;
4316 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
4319 power-domains = <&CLUSTER_PD>;
4321 apps_bcm_voter: bcm-voter {
4322 compatible = "qcom,bcm-voter";
4325 rpmhcc: clock-controller {
4326 compatible = "qcom,sc8280xp-rpmh-clk";
4327 #clock-cells = <1>;
4328 clock-names = "xo";
4332 rpmhpd: power-controller {
4333 compatible = "qcom,sc8280xp-rpmhpd";
4334 #power-domain-cells = <1>;
4335 operating-points-v2 = <&rpmhpd_opp_table>;
4337 rpmhpd_opp_table: opp-table {
4338 compatible = "operating-points-v2";
4341 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4345 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4349 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4353 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4357 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4361 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4365 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4369 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4373 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4377 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4384 compatible = "qcom,sc8280xp-epss-l3", "qcom,epss-l3";
4388 clock-names = "xo", "alternate";
4390 #interconnect-cells = <1>;
4394 compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss";
4397 reg-names = "freq-domain0", "freq-domain1";
4400 clock-names = "xo", "alternate";
4402 #freq-domain-cells = <1>;
4403 #clock-cells = <1>;
4407 compatible = "qcom,sc8280xp-nsp0-pas";
4410 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
4415 interrupt-names = "wdog", "fatal", "ready",
4416 "handover", "stop-ack";
4419 clock-names = "xo";
4421 power-domains = <&rpmhpd SC8280XP_NSP>;
4422 power-domain-names = "nsp";
4424 memory-region = <&pil_nsp0_mem>;
4426 qcom,smem-states = <&smp2p_nsp0_out 0>;
4427 qcom,smem-state-names = "stop";
4433 glink-edge {
4434 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
4441 qcom,remote-pid = <5>;
4445 qcom,glink-channels = "fastrpcglink-apps-dsp";
4447 #address-cells = <1>;
4448 #size-cells = <0>;
4450 compute-cb@1 {
4451 compatible = "qcom,fastrpc-compute-cb";
4456 compute-cb@2 {
4457 compatible = "qcom,fastrpc-compute-cb";
4462 compute-cb@3 {
4463 compatible = "qcom,fastrpc-compute-cb";
4468 compute-cb@4 {
4469 compatible = "qcom,fastrpc-compute-cb";
4474 compute-cb@5 {
4475 compatible = "qcom,fastrpc-compute-cb";
4480 compute-cb@6 {
4481 compatible = "qcom,fastrpc-compute-cb";
4486 compute-cb@7 {
4487 compatible = "qcom,fastrpc-compute-cb";
4492 compute-cb@8 {
4493 compatible = "qcom,fastrpc-compute-cb";
4498 compute-cb@9 {
4499 compatible = "qcom,fastrpc-compute-cb";
4504 compute-cb@10 {
4505 compatible = "qcom,fastrpc-compute-cb";
4510 compute-cb@11 {
4511 compatible = "qcom,fastrpc-compute-cb";
4516 compute-cb@12 {
4517 compatible = "qcom,fastrpc-compute-cb";
4522 compute-cb@13 {
4523 compatible = "qcom,fastrpc-compute-cb";
4528 compute-cb@14 {
4529 compatible = "qcom,fastrpc-compute-cb";
4538 compatible = "qcom,sc8280xp-nsp1-pas";
4541 interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>,
4546 interrupt-names = "wdog", "fatal", "ready",
4547 "handover", "stop-ack";
4550 clock-names = "xo";
4552 power-domains = <&rpmhpd SC8280XP_NSP>;
4553 power-domain-names = "nsp";
4555 memory-region = <&pil_nsp1_mem>;
4557 qcom,smem-states = <&smp2p_nsp1_out 0>;
4558 qcom,smem-state-names = "stop";
4564 glink-edge {
4565 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
4572 qcom,remote-pid = <12>;
4576 mdss1: display-subsystem@22000000 {
4577 compatible = "qcom,sc8280xp-mdss";
4579 reg-names = "mdss";
4584 clock-names = "iface",
4589 interconnect-names = "mdp0-mem", "mdp1-mem";
4593 power-domains = <&dispcc1 MDSS_GDSC>;
4596 interrupt-controller;
4597 #interrupt-cells = <1>;
4598 #address-cells = <2>;
4599 #size-cells = <2>;
4604 mdss1_mdp: display-controller@22001000 {
4605 compatible = "qcom,sc8280xp-dpu";
4608 reg-names = "mdp", "vbif";
4616 clock-names = "bus",
4622 interrupt-parent = <&mdss1>;
4624 power-domains = <&rpmhpd SC8280XP_MMCX>;
4626 assigned-clocks = <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>;
4627 assigned-clock-rates = <19200000>;
4628 operating-points-v2 = <&mdss1_mdp_opp_table>;
4631 #address-cells = <1>;
4632 #size-cells = <0>;
4637 remote-endpoint = <&mdss1_dp0_in>;
4644 remote-endpoint = <&mdss1_dp1_in>;
4651 remote-endpoint = <&mdss1_dp3_in>;
4658 remote-endpoint = <&mdss1_dp2_in>;
4663 mdss1_mdp_opp_table: opp-table {
4664 compatible = "operating-points-v2";
4666 opp-200000000 {
4667 opp-hz = /bits/ 64 <200000000>;
4668 required-opps = <&rpmhpd_opp_low_svs>;
4671 opp-300000000 {
4672 opp-hz = /bits/ 64 <300000000>;
4673 required-opps = <&rpmhpd_opp_svs>;
4676 opp-375000000 {
4677 opp-hz = /bits/ 64 <375000000>;
4678 required-opps = <&rpmhpd_opp_svs_l1>;
4681 opp-500000000 {
4682 opp-hz = /bits/ 64 <500000000>;
4683 required-opps = <&rpmhpd_opp_nom>;
4685 opp-600000000 {
4686 opp-hz = /bits/ 64 <600000000>;
4687 required-opps = <&rpmhpd_opp_turbo_l1>;
4692 mdss1_dp0: displayport-controller@22090000 {
4693 compatible = "qcom,sc8280xp-dp";
4705 clock-names = "core_iface", "core_aux",
4708 interrupt-parent = <&mdss1>;
4711 phy-names = "dp";
4712 power-domains = <&rpmhpd SC8280XP_MMCX>;
4714 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
4716 assigned-clock-parents = <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>;
4717 operating-points-v2 = <&mdss1_dp0_opp_table>;
4719 #sound-dai-cells = <0>;
4724 #address-cells = <1>;
4725 #size-cells = <0>;
4730 remote-endpoint = <&mdss1_intf0_out>;
4739 mdss1_dp0_opp_table: opp-table {
4740 compatible = "operating-points-v2";
4742 opp-160000000 {
4743 opp-hz = /bits/ 64 <160000000>;
4744 required-opps = <&rpmhpd_opp_low_svs>;
4747 opp-270000000 {
4748 opp-hz = /bits/ 64 <270000000>;
4749 required-opps = <&rpmhpd_opp_svs>;
4752 opp-540000000 {
4753 opp-hz = /bits/ 64 <540000000>;
4754 required-opps = <&rpmhpd_opp_svs_l1>;
4757 opp-810000000 {
4758 opp-hz = /bits/ 64 <810000000>;
4759 required-opps = <&rpmhpd_opp_nom>;
4764 mdss1_dp1: displayport-controller@22098000 {
4765 compatible = "qcom,sc8280xp-dp";
4777 clock-names = "core_iface", "core_aux",
4780 interrupt-parent = <&mdss1>;
4783 phy-names = "dp";
4784 power-domains = <&rpmhpd SC8280XP_MMCX>;
4786 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
4788 assigned-clock-parents = <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>;
4789 operating-points-v2 = <&mdss1_dp1_opp_table>;
4791 #sound-dai-cells = <0>;
4796 #address-cells = <1>;
4797 #size-cells = <0>;
4802 remote-endpoint = <&mdss1_intf4_out>;
4811 mdss1_dp1_opp_table: opp-table {
4812 compatible = "operating-points-v2";
4814 opp-160000000 {
4815 opp-hz = /bits/ 64 <160000000>;
4816 required-opps = <&rpmhpd_opp_low_svs>;
4819 opp-270000000 {
4820 opp-hz = /bits/ 64 <270000000>;
4821 required-opps = <&rpmhpd_opp_svs>;
4824 opp-540000000 {
4825 opp-hz = /bits/ 64 <540000000>;
4826 required-opps = <&rpmhpd_opp_svs_l1>;
4829 opp-810000000 {
4830 opp-hz = /bits/ 64 <810000000>;
4831 required-opps = <&rpmhpd_opp_nom>;
4836 mdss1_dp2: displayport-controller@2209a000 {
4837 compatible = "qcom,sc8280xp-dp";
4849 clock-names = "core_iface", "core_aux",
4852 interrupt-parent = <&mdss1>;
4855 phy-names = "dp";
4856 power-domains = <&rpmhpd SC8280XP_MMCX>;
4858 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
4860 assigned-clock-parents = <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>;
4861 operating-points-v2 = <&mdss1_dp2_opp_table>;
4863 #sound-dai-cells = <0>;
4868 #address-cells = <1>;
4869 #size-cells = <0>;
4874 remote-endpoint = <&mdss1_intf6_out>;
4883 mdss1_dp2_opp_table: opp-table {
4884 compatible = "operating-points-v2";
4886 opp-160000000 {
4887 opp-hz = /bits/ 64 <160000000>;
4888 required-opps = <&rpmhpd_opp_low_svs>;
4891 opp-270000000 {
4892 opp-hz = /bits/ 64 <270000000>;
4893 required-opps = <&rpmhpd_opp_svs>;
4896 opp-540000000 {
4897 opp-hz = /bits/ 64 <540000000>;
4898 required-opps = <&rpmhpd_opp_svs_l1>;
4901 opp-810000000 {
4902 opp-hz = /bits/ 64 <810000000>;
4903 required-opps = <&rpmhpd_opp_nom>;
4908 mdss1_dp3: displayport-controller@220a0000 {
4909 compatible = "qcom,sc8280xp-dp";
4921 clock-names = "core_iface", "core_aux",
4924 interrupt-parent = <&mdss1>;
4927 phy-names = "dp";
4928 power-domains = <&rpmhpd SC8280XP_MMCX>;
4930 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
4932 assigned-clock-parents = <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>;
4933 operating-points-v2 = <&mdss1_dp3_opp_table>;
4935 #sound-dai-cells = <0>;
4940 #address-cells = <1>;
4941 #size-cells = <0>;
4946 remote-endpoint = <&mdss1_intf5_out>;
4955 mdss1_dp3_opp_table: opp-table {
4956 compatible = "operating-points-v2";
4958 opp-160000000 {
4959 opp-hz = /bits/ 64 <160000000>;
4960 required-opps = <&rpmhpd_opp_low_svs>;
4963 opp-270000000 {
4964 opp-hz = /bits/ 64 <270000000>;
4965 required-opps = <&rpmhpd_opp_svs>;
4968 opp-540000000 {
4969 opp-hz = /bits/ 64 <540000000>;
4970 required-opps = <&rpmhpd_opp_svs_l1>;
4973 opp-810000000 {
4974 opp-hz = /bits/ 64 <810000000>;
4975 required-opps = <&rpmhpd_opp_nom>;
4982 compatible = "qcom,sc8280xp-dp-phy";
4990 clock-names = "aux", "cfg_ahb";
4991 power-domains = <&rpmhpd SC8280XP_MX>;
4993 #clock-cells = <1>;
4994 #phy-cells = <0>;
5000 compatible = "qcom,sc8280xp-dp-phy";
5008 clock-names = "aux", "cfg_ahb";
5009 power-domains = <&rpmhpd SC8280XP_MX>;
5011 #clock-cells = <1>;
5012 #phy-cells = <0>;
5017 dispcc1: clock-controller@22100000 {
5018 compatible = "qcom,sc8280xp-dispcc1";
5036 power-domains = <&rpmhpd SC8280XP_MMCX>;
5038 #clock-cells = <1>;
5039 #power-domain-cells = <1>;
5040 #reset-cells = <1>;
5046 compatible = "qcom,sc8280xp-ethqos";
5049 reg-names = "stmmaceth", "rgmii";
5055 clock-names = "stmmaceth",
5062 interrupt-names = "macirq", "eth_lpi";
5065 power-domains = <&gcc EMAC_1_GDSC>;
5069 rx-fifo-depth = <4096>;
5070 tx-fifo-depth = <4096>;
5079 thermal-zones {
5080 cpu0-thermal {
5081 polling-delay-passive = <250>;
5082 polling-delay = <1000>;
5084 thermal-sensors = <&tsens0 1>;
5087 cpu-crit {
5095 cpu1-thermal {
5096 polling-delay-passive = <250>;
5097 polling-delay = <1000>;
5099 thermal-sensors = <&tsens0 2>;
5102 cpu-crit {
5110 cpu2-thermal {
5111 polling-delay-passive = <250>;
5112 polling-delay = <1000>;
5114 thermal-sensors = <&tsens0 3>;
5117 cpu-crit {
5125 cpu3-thermal {
5126 polling-delay-passive = <250>;
5127 polling-delay = <1000>;
5129 thermal-sensors = <&tsens0 4>;
5132 cpu-crit {
5140 cpu4-thermal {
5141 polling-delay-passive = <250>;
5142 polling-delay = <1000>;
5144 thermal-sensors = <&tsens0 5>;
5147 cpu-crit {
5155 cpu5-thermal {
5156 polling-delay-passive = <250>;
5157 polling-delay = <1000>;
5159 thermal-sensors = <&tsens0 6>;
5162 cpu-crit {
5170 cpu6-thermal {
5171 polling-delay-passive = <250>;
5172 polling-delay = <1000>;
5174 thermal-sensors = <&tsens0 7>;
5177 cpu-crit {
5185 cpu7-thermal {
5186 polling-delay-passive = <250>;
5187 polling-delay = <1000>;
5189 thermal-sensors = <&tsens0 8>;
5192 cpu-crit {
5200 cluster0-thermal {
5201 polling-delay-passive = <250>;
5202 polling-delay = <1000>;
5204 thermal-sensors = <&tsens0 9>;
5207 cpu-crit {
5215 mem-thermal {
5216 polling-delay-passive = <250>;
5217 polling-delay = <1000>;
5219 thermal-sensors = <&tsens1 15>;
5222 trip-point0 {
5232 compatible = "arm,armv8-timer";