Lines Matching +full:ipq8074 +full:- +full:tsens
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
9 #include <dt-bindings/clock/qcom,apss-ipq.h>
10 #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&intc>;
17 #address-cells = <2>;
18 #size-cells = <2>;
21 sleep_clk: sleep-clk {
22 compatible = "fixed-clock";
23 #clock-cells = <0>;
26 xo_board_clk: xo-board-clk {
27 compatible = "fixed-clock";
28 #clock-cells = <0>;
33 #address-cells = <1>;
34 #size-cells = <0>;
38 compatible = "arm,cortex-a73";
40 enable-method = "psci";
41 next-level-cache = <&L2_0>;
43 clock-names = "cpu";
44 operating-points-v2 = <&cpu_opp_table>;
45 cpu-supply = <&ipq9574_s1>;
46 #cooling-cells = <2>;
51 compatible = "arm,cortex-a73";
53 enable-method = "psci";
54 next-level-cache = <&L2_0>;
56 clock-names = "cpu";
57 operating-points-v2 = <&cpu_opp_table>;
58 cpu-supply = <&ipq9574_s1>;
59 #cooling-cells = <2>;
64 compatible = "arm,cortex-a73";
66 enable-method = "psci";
67 next-level-cache = <&L2_0>;
69 clock-names = "cpu";
70 operating-points-v2 = <&cpu_opp_table>;
71 cpu-supply = <&ipq9574_s1>;
72 #cooling-cells = <2>;
77 compatible = "arm,cortex-a73";
79 enable-method = "psci";
80 next-level-cache = <&L2_0>;
82 clock-names = "cpu";
83 operating-points-v2 = <&cpu_opp_table>;
84 cpu-supply = <&ipq9574_s1>;
85 #cooling-cells = <2>;
88 L2_0: l2-cache {
90 cache-level = <2>;
91 cache-unified;
97 compatible = "qcom,scm-ipq9574", "qcom,scm";
98 qcom,dload-mode = <&tcsr 0x6100>;
108 cpu_opp_table: opp-table-cpu {
109 compatible = "operating-points-v2-kryo-cpu";
110 opp-shared;
111 nvmem-cells = <&cpu_speed_bin>;
113 opp-936000000 {
114 opp-hz = /bits/ 64 <936000000>;
115 opp-microvolt = <725000>;
116 opp-supported-hw = <0xf>;
117 clock-latency-ns = <200000>;
120 opp-1104000000 {
121 opp-hz = /bits/ 64 <1104000000>;
122 opp-microvolt = <787500>;
123 opp-supported-hw = <0xf>;
124 clock-latency-ns = <200000>;
127 opp-1200000000 {
128 opp-hz = /bits/ 64 <1200000000>;
129 opp-microvolt = <862500>;
130 opp-supported-hw = <0xf>;
131 clock-latency-ns = <200000>;
134 opp-1416000000 {
135 opp-hz = /bits/ 64 <1416000000>;
136 opp-microvolt = <862500>;
137 opp-supported-hw = <0x7>;
138 clock-latency-ns = <200000>;
141 opp-1488000000 {
142 opp-hz = /bits/ 64 <1488000000>;
143 opp-microvolt = <925000>;
144 opp-supported-hw = <0x7>;
145 clock-latency-ns = <200000>;
148 opp-1800000000 {
149 opp-hz = /bits/ 64 <1800000000>;
150 opp-microvolt = <987500>;
151 opp-supported-hw = <0x5>;
152 clock-latency-ns = <200000>;
155 opp-2208000000 {
156 opp-hz = /bits/ 64 <2208000000>;
157 opp-microvolt = <1062500>;
158 opp-supported-hw = <0x1>;
159 clock-latency-ns = <200000>;
164 compatible = "arm,cortex-a73-pmu";
169 compatible = "arm,psci-1.0";
174 compatible = "qcom,ipq9574-rpm-proc", "qcom,rpm-proc";
176 glink-edge {
177 compatible = "qcom,glink-rpm";
179 qcom,rpm-msg-ram = <&rpm_msg_ram>;
182 rpm_requests: rpm-requests {
183 compatible = "qcom,rpm-ipq9574";
184 qcom,glink-channels = "rpm_requests";
189 reserved-memory {
190 #address-cells = <2>;
191 #size-cells = <2>;
196 no-map;
201 no-map;
206 no-map;
213 no-map;
218 compatible = "simple-bus";
219 #address-cells = <1>;
220 #size-cells = <1>;
224 compatible = "qcom,rpm-msg-ram";
229 compatible = "qcom,prng-ee";
232 clock-names = "core";
236 compatible = "qcom,ipq9574-qfprom", "qcom,qfprom";
238 #address-cells = <1>;
239 #size-cells = <1>;
241 cpu_speed_bin: cpu-speed-bin@15 {
247 cryptobam: dma-controller@704000 {
248 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
251 #dma-cells = <1>;
253 qcom,controlled-remotely;
257 compatible = "qcom,ipq9574-qce", "qcom,ipq4019-qce", "qcom,qce";
262 clock-names = "iface", "bus", "core";
264 dma-names = "rx", "tx";
267 tsens: thermal-sensor@4a9000 {
268 compatible = "qcom,ipq9574-tsens", "qcom,ipq8074-tsens";
272 interrupt-names = "combined";
274 #thermal-sensor-cells = <1>;
278 compatible = "qcom,ipq9574-tlmm";
281 gpio-controller;
282 #gpio-cells = <2>;
283 gpio-ranges = <&tlmm 0 0 65>;
284 interrupt-controller;
285 #interrupt-cells = <2>;
287 uart2_pins: uart2-state {
290 drive-strength = <8>;
291 bias-disable;
295 gcc: clock-controller@1800000 {
296 compatible = "qcom,ipq9574-gcc";
306 #clock-cells = <1>;
307 #reset-cells = <1>;
308 #power-domain-cells = <1>;
312 compatible = "qcom,tcsr-mutex";
314 #hwlock-cells = <1>;
318 compatible = "qcom,tcsr-ipq9574", "syscon";
323 compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5";
325 reg-names = "hc", "cqhci";
329 interrupt-names = "hc_irq", "pwr_irq";
334 clock-names = "iface", "core", "xo";
335 non-removable;
339 blsp_dma: dma-controller@7884000 {
340 compatible = "qcom,bam-v1.7.0";
344 clock-names = "bam_clk";
345 #dma-cells = <1>;
350 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
355 clock-names = "core", "iface";
360 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
365 clock-names = "core", "iface";
370 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
375 clock-names = "core", "iface";
380 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
385 clock-names = "core", "iface";
390 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
395 clock-names = "core", "iface";
400 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
405 clock-names = "core", "iface";
410 compatible = "qcom,spi-qup-v2.2.1";
412 #address-cells = <1>;
413 #size-cells = <0>;
417 clock-names = "core", "iface";
419 dma-names = "tx", "rx";
424 compatible = "qcom,i2c-qup-v2.2.1";
426 #address-cells = <1>;
427 #size-cells = <0>;
431 clock-names = "core", "iface";
432 assigned-clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
433 assigned-clock-rates = <50000000>;
435 dma-names = "tx", "rx";
440 compatible = "qcom,spi-qup-v2.2.1";
442 #address-cells = <1>;
443 #size-cells = <0>;
447 clock-names = "core", "iface";
449 dma-names = "tx", "rx";
454 compatible = "qcom,i2c-qup-v2.2.1";
456 #address-cells = <1>;
457 #size-cells = <0>;
461 clock-names = "core", "iface";
462 assigned-clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
463 assigned-clock-rates = <50000000>;
465 dma-names = "tx", "rx";
470 compatible = "qcom,spi-qup-v2.2.1";
472 #address-cells = <1>;
473 #size-cells = <0>;
477 clock-names = "core", "iface";
479 dma-names = "tx", "rx";
484 compatible = "qcom,i2c-qup-v2.2.1";
486 #address-cells = <1>;
487 #size-cells = <0>;
491 clock-names = "core", "iface";
492 assigned-clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
493 assigned-clock-rates = <50000000>;
495 dma-names = "tx", "rx";
500 compatible = "qcom,spi-qup-v2.2.1";
502 #address-cells = <1>;
503 #size-cells = <0>;
505 spi-max-frequency = <50000000>;
508 clock-names = "core", "iface";
510 dma-names = "tx", "rx";
515 compatible = "qcom,i2c-qup-v2.2.1";
517 #address-cells = <1>;
518 #size-cells = <0>;
522 clock-names = "core", "iface";
523 assigned-clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
524 assigned-clock-rates = <50000000>;
526 dma-names = "tx", "rx";
531 compatible = "qcom,spi-qup-v2.2.1";
533 #address-cells = <1>;
534 #size-cells = <0>;
538 clock-names = "core", "iface";
540 dma-names = "tx", "rx";
545 compatible = "qcom,ipq9574-qusb2-phy";
547 #phy-cells = <0>;
551 clock-names = "cfg_ahb",
559 compatible = "qcom,ipq9574-qmp-usb3-phy";
561 #phy-cells = <0>;
567 clock-names = "aux",
574 reset-names = "phy",
577 #clock-cells = <0>;
578 clock-output-names = "usb0_pipe_clk";
584 compatible = "qcom,ipq9574-dwc3", "qcom,dwc3";
586 #address-cells = <1>;
587 #size-cells = <1>;
596 clock-names = "cfg_noc",
602 assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
604 assigned-clock-rates = <200000000>,
607 interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
608 interrupt-names = "pwr_event";
617 clock-names = "ref";
620 phy-names = "usb2-phy", "usb3-phy";
621 tx-fifo-resize;
622 snps,is-utmi-l1-suspend;
623 snps,hird-threshold = /bits/ 8 <0x0>;
629 intc: interrupt-controller@b000000 {
630 compatible = "qcom,msm-qgic2";
635 #address-cells = <1>;
636 #size-cells = <1>;
637 interrupt-controller;
638 #interrupt-cells = <3>;
643 compatible = "arm,gic-v2m-frame";
645 msi-controller;
649 compatible = "arm,gic-v2m-frame";
651 msi-controller;
655 compatible = "arm,gic-v2m-frame";
657 msi-controller;
662 compatible = "qcom,apss-wdt-ipq9574", "qcom,kpss-wdt";
666 timeout-sec = <30>;
670 compatible = "qcom,ipq9574-apcs-apps-global",
671 "qcom,ipq6018-apcs-apps-global";
673 #clock-cells = <1>;
675 clock-names = "pll", "xo", "gpll0";
676 #mbox-cells = <1>;
680 compatible = "qcom,ipq9574-a73pll";
682 #clock-cells = <0>;
684 clock-names = "xo";
688 compatible = "arm,armv7-timer-mem";
690 #address-cells = <1>;
691 #size-cells = <1>;
697 frame-number = <0>;
704 frame-number = <1>;
711 frame-number = <2>;
718 frame-number = <3>;
725 frame-number = <4>;
732 frame-number = <5>;
739 frame-number = <6>;
746 thermal-zones {
747 nss-top-thermal {
748 polling-delay-passive = <0>;
749 polling-delay = <0>;
750 thermal-sensors = <&tsens 3>;
753 nss-top-critical {
761 ubi-0-thermal {
762 polling-delay-passive = <0>;
763 polling-delay = <0>;
764 thermal-sensors = <&tsens 4>;
767 ubi_0-critical {
775 ubi-1-thermal {
776 polling-delay-passive = <0>;
777 polling-delay = <0>;
778 thermal-sensors = <&tsens 5>;
781 ubi_1-critical {
789 ubi-2-thermal {
790 polling-delay-passive = <0>;
791 polling-delay = <0>;
792 thermal-sensors = <&tsens 6>;
795 ubi_2-critical {
803 ubi-3-thermal {
804 polling-delay-passive = <0>;
805 polling-delay = <0>;
806 thermal-sensors = <&tsens 7>;
809 ubi_3-critical {
817 cpuss0-thermal {
818 polling-delay-passive = <0>;
819 polling-delay = <0>;
820 thermal-sensors = <&tsens 8>;
823 cpu-critical {
831 cpuss1-thermal {
832 polling-delay-passive = <0>;
833 polling-delay = <0>;
834 thermal-sensors = <&tsens 9>;
837 cpu-critical {
845 cpu0-thermal {
846 polling-delay-passive = <0>;
847 polling-delay = <0>;
848 thermal-sensors = <&tsens 10>;
851 cpu0_crit: cpu-critical {
857 cpu0_alert: cpu-passive {
864 cooling-maps {
867 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
875 cpu1-thermal {
876 polling-delay-passive = <0>;
877 polling-delay = <0>;
878 thermal-sensors = <&tsens 11>;
881 cpu1_crit: cpu-critical {
887 cpu1_alert: cpu-passive {
894 cooling-maps {
897 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
905 cpu2-thermal {
906 polling-delay-passive = <0>;
907 polling-delay = <0>;
908 thermal-sensors = <&tsens 12>;
911 cpu2_crit: cpu-critical {
917 cpu2_alert: cpu-passive {
924 cooling-maps {
927 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
935 cpu3-thermal {
936 polling-delay-passive = <0>;
937 polling-delay = <0>;
938 thermal-sensors = <&tsens 13>;
941 cpu3_crit: cpu-critical {
947 cpu3_alert: cpu-passive {
954 cooling-maps {
957 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
965 wcss-phyb-thermal {
966 polling-delay-passive = <0>;
967 polling-delay = <0>;
968 thermal-sensors = <&tsens 14>;
971 wcss_phyb-critical {
979 top-glue-thermal {
980 polling-delay-passive = <0>;
981 polling-delay = <0>;
982 thermal-sensors = <&tsens 15>;
985 top_glue-critical {
995 compatible = "arm,armv8-timer";