Lines Matching +full:psci +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0+
8 #include <dt-bindings/clock/mt6779-clk.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/mt6779-pinfunc.h>
15 interrupt-parent = <&sysirq>;
16 #address-cells = <2>;
17 #size-cells = <2>;
19 psci {
20 compatible = "arm,psci-0.2";
25 #address-cells = <1>;
26 #size-cells = <0>;
28 cpu0: cpu@0 {
30 compatible = "arm,cortex-a55";
31 enable-method = "psci";
32 reg = <0x000>;
37 compatible = "arm,cortex-a55";
38 enable-method = "psci";
39 reg = <0x100>;
44 compatible = "arm,cortex-a55";
45 enable-method = "psci";
46 reg = <0x200>;
51 compatible = "arm,cortex-a55";
52 enable-method = "psci";
53 reg = <0x300>;
58 compatible = "arm,cortex-a55";
59 enable-method = "psci";
60 reg = <0x400>;
65 compatible = "arm,cortex-a55";
66 enable-method = "psci";
67 reg = <0x500>;
72 compatible = "arm,cortex-a75";
73 enable-method = "psci";
74 reg = <0x600>;
79 compatible = "arm,cortex-a75";
80 enable-method = "psci";
81 reg = <0x700>;
86 compatible = "arm,armv8-pmuv3";
87 interrupt-parent = <&gic>;
88 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW 0>;
91 clk26m: oscillator-26m {
92 compatible = "fixed-clock";
93 #clock-cells = <0>;
94 clock-frequency = <26000000>;
95 clock-output-names = "clk26m";
98 clk32k: oscillator-32k {
99 compatible = "fixed-clock";
100 #clock-cells = <0>;
101 clock-frequency = <32768>;
102 clock-output-names = "clk32k";
106 compatible = "arm,armv8-timer";
107 interrupt-parent = <&gic>;
108 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
109 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
110 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
111 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
115 #address-cells = <2>;
116 #size-cells = <2>;
117 compatible = "simple-bus";
120 gic: interrupt-controller@c000000 {
121 compatible = "arm,gic-v3";
122 #interrupt-cells = <4>;
123 interrupt-parent = <&gic>;
124 interrupt-controller;
125 reg = <0 0x0c000000 0 0x40000>, /* GICD */
126 <0 0x0c040000 0 0x200000>; /* GICR */
127 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
129 ppi-partitions {
130 ppi_cluster0: interrupt-partition-0 {
134 ppi_cluster1: interrupt-partition-1 {
141 sysirq: intpol-controller@c53a650 {
142 compatible = "mediatek,mt6779-sysirq",
143 "mediatek,mt6577-sysirq";
144 interrupt-controller;
145 #interrupt-cells = <3>;
146 interrupt-parent = <&gic>;
147 reg = <0 0x0c53a650 0 0x50>;
150 topckgen: clock-controller@10000000 {
151 compatible = "mediatek,mt6779-topckgen", "syscon";
152 reg = <0 0x10000000 0 0x1000>;
153 #clock-cells = <1>;
156 infracfg_ao: clock-controller@10001000 {
157 compatible = "mediatek,mt6779-infracfg_ao", "syscon";
158 reg = <0 0x10001000 0 0x1000>;
159 #clock-cells = <1>;
163 compatible = "mediatek,mt6779-pinctrl";
164 reg = <0 0x10005000 0 0x1000>,
165 <0 0x11c20000 0 0x1000>,
166 <0 0x11d10000 0 0x1000>,
167 <0 0x11e20000 0 0x1000>,
168 <0 0x11e70000 0 0x1000>,
169 <0 0x11ea0000 0 0x1000>,
170 <0 0x11f20000 0 0x1000>,
171 <0 0x11f30000 0 0x1000>,
172 <0 0x1000b000 0 0x1000>;
173 reg-names = "gpio", "iocfg_rm",
178 gpio-controller;
179 #gpio-cells = <2>;
180 gpio-ranges = <&pio 0 0 210>;
181 interrupt-controller;
182 #interrupt-cells = <2>;
186 apmixed: clock-controller@1000c000 {
187 compatible = "mediatek,mt6779-apmixed", "syscon";
188 reg = <0 0x1000c000 0 0xe00>;
189 #clock-cells = <1>;
193 compatible = "mediatek,mt6779-pwrap";
194 reg = <0 0x1000d000 0 0x1000>;
195 reg-names = "pwrap";
198 clock-names = "spi", "wrap";
202 compatible = "mediatek,mt6779-devapc";
203 reg = <0 0x10207000 0 0x1000>;
206 clock-names = "devapc-infra-clock";
210 compatible = "mediatek,mt6779-uart",
211 "mediatek,mt6577-uart";
212 reg = <0 0x11002000 0 0x400>;
215 clock-names = "baud", "bus";
220 compatible = "mediatek,mt6779-uart",
221 "mediatek,mt6577-uart";
222 reg = <0 0x11003000 0 0x400>;
225 clock-names = "baud", "bus";
230 compatible = "mediatek,mt6779-uart",
231 "mediatek,mt6577-uart";
232 reg = <0 0x11004000 0 0x400>;
235 clock-names = "baud", "bus";
239 audio: clock-controller@11210000 {
240 compatible = "mediatek,mt6779-audio", "syscon";
241 reg = <0 0x11210000 0 0x1000>;
242 #clock-cells = <1>;
245 mfgcfg: clock-controller@13fbf000 {
246 compatible = "mediatek,mt6779-mfgcfg", "syscon";
247 reg = <0 0x13fbf000 0 0x1000>;
248 #clock-cells = <1>;
252 compatible = "mediatek,mt6779-mmsys", "syscon";
253 reg = <0 0x14000000 0 0x1000>;
254 #clock-cells = <1>;
257 imgsys: clock-controller@15020000 {
258 compatible = "mediatek,mt6779-imgsys", "syscon";
259 reg = <0 0x15020000 0 0x1000>;
260 #clock-cells = <1>;
263 vdecsys: clock-controller@16000000 {
264 compatible = "mediatek,mt6779-vdecsys", "syscon";
265 reg = <0 0x16000000 0 0x1000>;
266 #clock-cells = <1>;
269 vencsys: clock-controller@17000000 {
270 compatible = "mediatek,mt6779-vencsys", "syscon";
271 reg = <0 0x17000000 0 0x1000>;
272 #clock-cells = <1>;
275 camsys: clock-controller@1a000000 {
276 compatible = "mediatek,mt6779-camsys", "syscon";
277 reg = <0 0x1a000000 0 0x10000>;
278 #clock-cells = <1>;
281 ipesys: clock-controller@1b000000 {
282 compatible = "mediatek,mt6779-ipesys", "syscon";
283 reg = <0 0x1b000000 0 0x1000>;
284 #clock-cells = <1>;