Lines Matching +full:mdio +full:- +full:gpio0
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 #address-cells = <2>;
21 #size-cells = <0>;
23 cpu-map {
36 compatible = "arm,cortex-a55";
38 enable-method = "psci";
39 next-level-cache = <&l2>;
44 compatible = "arm,cortex-a55";
46 enable-method = "psci";
47 next-level-cache = <&l2>;
50 l2: l2-cache {
52 cache-level = <2>;
53 cache-unified;
58 compatible = "arm,psci-0.2";
63 compatible = "arm,armv8-timer";
71 compatible = "arm,armv8-pmuv3";
76 compatible = "simple-bus";
77 #address-cells = <2>;
78 #size-cells = <2>;
80 dma-ranges;
82 internal-regs@7f000000 {
83 #address-cells = <1>;
84 #size-cells = <1>;
85 compatible = "simple-bus";
88 dma-coherent;
91 compatible = "snps,dw-apb-uart";
93 reg-shift = <2>;
95 reg-io-width = <1>;
101 compatible = "snps,dw-apb-uart";
103 reg-shift = <2>;
105 reg-io-width = <1>;
111 compatible = "snps,dw-apb-uart";
113 reg-shift = <2>;
115 reg-io-width = <1>;
121 compatible = "snps,dw-apb-uart";
123 reg-shift = <2>;
125 reg-io-width = <1>;
130 mdio: mdio@22004 {
131 #address-cells = <1>;
132 #size-cells = <0>;
133 compatible = "marvell,orion-mdio";
139 compatible = "marvell,mv78230-i2c";
141 #address-cells = <1>;
142 #size-cells = <0>;
145 clock-names = "core";
147 clock-frequency = <100000>;
149 pinctrl-names = "default", "gpio";
150 pinctrl-0 = <&i2c0_pins>;
151 pinctrl-1 = <&i2c0_gpio>;
152 scl-gpios = <&gpio0 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
153 sda-gpios = <&gpio0 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
158 compatible = "marvell,mv78230-i2c";
160 #address-cells = <1>;
161 #size-cells = <0>;
164 clock-names = "core";
166 clock-frequency = <100000>;
168 pinctrl-names = "default", "gpio";
169 pinctrl-0 = <&i2c1_pins>;
170 pinctrl-1 = <&i2c1_gpio>;
171 scl-gpios = <&gpio0 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
172 sda-gpios = <&gpio0 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
176 gpio0: gpio@18100 {
177 compatible = "marvell,orion-gpio";
180 gpio-controller;
181 #gpio-cells = <2>;
182 gpio-ranges = <&pinctrl0 0 0 32>;
183 marvell,pwm-offset = <0x1f0>;
184 interrupt-controller;
185 #interrupt-cells = <2>;
194 compatible = "marvell,orion-gpio";
196 gpio-controller;
197 #gpio-cells = <2>;
198 gpio-ranges = <&pinctrl0 0 32 14>;
199 marvell,pwm-offset = <0x1f0>;
200 interrupt-controller;
201 #interrupt-cells = <2>;
211 behind-32bit-controller@7f000000 {
212 compatible = "simple-bus";
213 #address-cells = <0x2>;
214 #size-cells = <0x2>;
217 dma-ranges = <0x0 0x0 0x2 0x0 0x1 0x0>;
218 dma-coherent;
221 compatible = "marvell,armada-ac5-neta";
225 phy-mode = "sgmii";
230 compatible = "marvell,armada-ac5-neta";
234 phy-mode = "sgmii";
239 compatible = "marvell,orion-ehci";
246 compatible = "marvell,orion-ehci";
254 compatible = "marvell,ac5-pinctrl";
257 i2c0_pins: i2c0-pins {
262 i2c0_gpio: i2c0-gpio-pins {
267 i2c1_pins: i2c1-pins {
272 i2c1_gpio: i2c1-gpio-pins {
279 compatible = "marvell,armada-3700-spi";
281 #address-cells = <0x1>;
282 #size-cells = <0x0>;
285 num-cs = <1>;
290 compatible = "marvell,armada-3700-spi";
292 #address-cells = <0x1>;
293 #size-cells = <0x0>;
296 num-cs = <1>;
300 nand: nand-controller@805b0000 {
301 compatible = "marvell,ac5-nand-controller";
303 #address-cells = <0x1>;
304 #size-cells = <0x0>;
310 gic: interrupt-controller@80600000 {
311 compatible = "arm,gic-v3";
312 #interrupt-cells = <3>;
313 interrupt-controller;
321 cnm_clock: cnm-clock {
322 compatible = "fixed-clock";
323 #clock-cells = <0>;
324 clock-frequency = <328000000>;
327 spi_clock: spi-clock {
328 compatible = "fixed-clock";
329 #clock-cells = <0>;
330 clock-frequency = <200000000>;
333 nand_clock: nand-clock {
334 compatible = "fixed-clock";
335 #clock-cells = <0>;
336 clock-frequency = <400000000>;