Lines Matching +full:mdio +full:- +full:gpio0

1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3  * Device Tree Include file for Freescale Layerscape-1046A family SoC.
6  * Copyright 2018-2019 NXP
11 /dts-v1/;
13 #include "fsl-ls1046a.dtsi"
17 	compatible = "fsl,ls1046a-qds", "fsl,ls1046a";
20 		emi1-slot1 = &ls1046mdio_s1;
21 		emi1-slot2 = &ls1046mdio_s2;
22 		emi1-slot4 = &ls1046mdio_s4;
23 		gpio0 = &gpio0;
27 		qsgmii-s2-p1 = &qsgmii_phy_s2_p1;
28 		qsgmii-s2-p2 = &qsgmii_phy_s2_p2;
29 		qsgmii-s2-p3 = &qsgmii_phy_s2_p3;
30 		qsgmii-s2-p4 = &qsgmii_phy_s2_p4;
35 		sgmii-s1-p1 = &sgmii_phy_s1_p1;
36 		sgmii-s1-p2 = &sgmii_phy_s1_p2;
37 		sgmii-s1-p3 = &sgmii_phy_s1_p3;
38 		sgmii-s1-p4 = &sgmii_phy_s1_p4;
39 		sgmii-s4-p1 = &sgmii_phy_s4_p1;
43 		stdout-path = "serial0:115200n8";
48 	bus-num = <0>;
52 		#address-cells = <1>;
53 		#size-cells = <1>;
54 		compatible = "n25q128a11", "jedec,spi-nor";
56 		spi-max-frequency = <10000000>;
60 		#address-cells = <1>;
61 		#size-cells = <1>;
62 		compatible = "sst25wf040b", "jedec,spi-nor";
63 		spi-cpol;
64 		spi-cpha;
66 		spi-max-frequency = <10000000>;
70 		#address-cells = <1>;
71 		#size-cells = <1>;
72 		compatible = "en25s64", "jedec,spi-nor";
73 		spi-cpol;
74 		spi-cpha;
76 		spi-max-frequency = <10000000>;
91 	i2c-mux@77 {
94 		#address-cells = <1>;
95 		#size-cells = <0>;
98 			#address-cells = <1>;
99 			#size-cells = <0>;
105 				shunt-resistor = <1000>;
111 				shunt-resistor = <1000>;
116 			#address-cells = <1>;
117 			#size-cells = <0>;
137 			temp-sensor@4c {
146 	#address-cells = <2>;
147 	#size-cells = <1>;
155 		compatible = "cfi-flash";
157 		big-endian;
158 		bank-width = <2>;
159 		device-width = <1>;
163 		compatible = "fsl,ifc-nand";
167 	fpga: board-control@2,0 {
168 		compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis", "simple-mfd";
183 		#address-cells = <1>;
184 		#size-cells = <1>;
185 		spi-max-frequency = <50000000>;
186 		spi-rx-bus-width = <4>;
187 		spi-tx-bus-width = <4>;
192 #include "fsl-ls1046-post.dtsi"
196 		phy-handle = <&qsgmii_phy_s2_p1>;
197 		phy-connection-type = "sgmii";
201 		phy-handle = <&sgmii_phy_s4_p1>;
202 		phy-connection-type = "sgmii";
206 		phy-handle = <&rgmii_phy1>;
207 		phy-connection-type = "rgmii";
211 		phy-handle = <&rgmii_phy2>;
212 		phy-connection-type = "rgmii";
216 		phy-handle = <&sgmii_phy_s1_p3>;
217 		phy-connection-type = "sgmii";
221 		phy-handle = <&sgmii_phy_s1_p4>;
222 		phy-connection-type = "sgmii";
226 		phy-handle = <&sgmii_phy_s1_p1>;
227 		phy-connection-type = "xgmii";
231 		phy-handle = <&sgmii_phy_s1_p2>;
232 		phy-connection-type = "xgmii";
237 	#address-cells = <1>;
238 	#size-cells = <1>;
240 	mdio-mux-emi1 {
241 		compatible = "mdio-mux-mmioreg", "mdio-mux";
242 		mdio-parent-bus = <&mdio0>;
243 		#address-cells = <1>;
244 		#size-cells = <0>;
246 		mux-mask = <0xe0>; /* EMI1 */
248 		/* On-board RGMII1 PHY */
249 		ls1046mdio0: mdio@0 {
251 			#address-cells = <1>;
252 			#size-cells = <0>;
254 			rgmii_phy1: ethernet-phy@1 { /* MAC3 */
259 		/* On-board RGMII2 PHY */
260 		ls1046mdio1: mdio@1 {
262 			#address-cells = <1>;
263 			#size-cells = <0>;
265 			rgmii_phy2: ethernet-phy@2 { /* MAC4 */
271 		ls1046mdio_s1: mdio@2 {
273 			#address-cells = <1>;
274 			#size-cells = <0>;
277 			sgmii_phy_s1_p1: ethernet-phy@1c {
281 			sgmii_phy_s1_p2: ethernet-phy@1d {
285 			sgmii_phy_s1_p3: ethernet-phy@1e {
289 			sgmii_phy_s1_p4: ethernet-phy@1f {
295 		ls1046mdio_s2: mdio@3 {
297 			#address-cells = <1>;
298 			#size-cells = <0>;
301 			qsgmii_phy_s2_p1: ethernet-phy@8 {
305 			qsgmii_phy_s2_p2: ethernet-phy@9 {
309 			qsgmii_phy_s2_p3: ethernet-phy@a {
313 			qsgmii_phy_s2_p4: ethernet-phy@b {
319 		ls1046mdio_s4: mdio@5 {
321 			#address-cells = <1>;
322 			#size-cells = <0>;
325 			sgmii_phy_s4_p1: ethernet-phy@1c {