Lines Matching +full:cpu +full:- +full:capacity
1 // SPDX-License-Identifier: BSD-3-Clause
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/cix,sky1.h>
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <2>;
17 #size-cells = <0>;
19 cpu0: cpu@0 {
20 compatible = "arm,cortex-a520";
21 enable-method = "psci";
23 device_type = "cpu";
24 capacity-dmips-mhz = <403>;
27 cpu1: cpu@100 {
28 compatible = "arm,cortex-a520";
29 enable-method = "psci";
31 device_type = "cpu";
32 capacity-dmips-mhz = <403>;
35 cpu2: cpu@200 {
36 compatible = "arm,cortex-a520";
37 enable-method = "psci";
39 device_type = "cpu";
40 capacity-dmips-mhz = <403>;
43 cpu3: cpu@300 {
44 compatible = "arm,cortex-a520";
45 enable-method = "psci";
47 device_type = "cpu";
48 capacity-dmips-mhz = <403>;
51 cpu4: cpu@400 {
52 compatible = "arm,cortex-a720";
53 enable-method = "psci";
55 device_type = "cpu";
56 capacity-dmips-mhz = <1024>;
59 cpu5: cpu@500 {
60 compatible = "arm,cortex-a720";
61 enable-method = "psci";
63 device_type = "cpu";
64 capacity-dmips-mhz = <1024>;
67 cpu6: cpu@600 {
68 compatible = "arm,cortex-a720";
69 enable-method = "psci";
71 device_type = "cpu";
72 capacity-dmips-mhz = <1024>;
75 cpu7: cpu@700 {
76 compatible = "arm,cortex-a720";
77 enable-method = "psci";
79 device_type = "cpu";
80 capacity-dmips-mhz = <1024>;
83 cpu8: cpu@800 {
84 compatible = "arm,cortex-a720";
85 enable-method = "psci";
87 device_type = "cpu";
88 capacity-dmips-mhz = <1024>;
91 cpu9: cpu@900 {
92 compatible = "arm,cortex-a720";
93 enable-method = "psci";
95 device_type = "cpu";
96 capacity-dmips-mhz = <1024>;
99 cpu10: cpu@a00 {
100 compatible = "arm,cortex-a720";
101 enable-method = "psci";
103 device_type = "cpu";
104 capacity-dmips-mhz = <1024>;
107 cpu11: cpu@b00 {
108 compatible = "arm,cortex-a720";
109 enable-method = "psci";
111 device_type = "cpu";
112 capacity-dmips-mhz = <1024>;
115 cpu-map {
118 cpu = <&cpu0>;
121 cpu = <&cpu1>;
124 cpu = <&cpu2>;
127 cpu = <&cpu3>;
130 cpu = <&cpu4>;
133 cpu = <&cpu5>;
136 cpu = <&cpu6>;
139 cpu = <&cpu7>;
142 cpu = <&cpu8>;
145 cpu = <&cpu9>;
148 cpu = <&cpu10>;
151 cpu = <&cpu11>;
160 mbox-names = "tx", "rx";
163 #address-cells = <1>;
164 #size-cells = <0>;
168 #clock-cells = <1>;
173 pmu-a520 {
174 compatible = "arm,cortex-a520-pmu";
178 pmu-a720 {
179 compatible = "arm,cortex-a720-pmu";
184 compatible = "arm,psci-1.0";
189 compatible = "simple-bus";
191 dma-ranges;
192 #address-cells = <2>;
193 #size-cells = <2>;
200 clock-names = "uartclk", "apb_pclk";
209 clock-names = "uartclk", "apb_pclk";
218 clock-names = "uartclk", "apb_pclk";
227 clock-names = "uartclk", "apb_pclk";
232 compatible = "cix,sky1-mbox";
235 #mbox-cells = <1>;
236 cix,mbox-dir = "tx";
240 compatible = "cix,sky1-mbox";
243 #mbox-cells = <1>;
244 cix,mbox-dir = "rx";
248 compatible = "arm,scmi-shmem";
250 reg-io-width = <4>;
254 compatible = "cix,sky1-mbox";
257 #mbox-cells = <1>;
258 cix,mbox-dir = "tx";
262 compatible = "arm,scmi-shmem";
264 reg-io-width = <4>;
268 compatible = "cix,sky1-mbox";
271 #mbox-cells = <1>;
272 cix,mbox-dir = "rx";
276 compatible = "cix,sky1-mbox";
279 #mbox-cells = <1>;
280 cix,mbox-dir = "rx";
284 compatible = "cix,sky1-mbox";
287 #mbox-cells = <1>;
288 cix,mbox-dir = "tx";
291 gic: interrupt-controller@e010000 {
292 compatible = "arm,gic-v3";
296 #interrupt-cells = <4>;
297 interrupt-controller;
298 #address-cells = <2>;
299 #size-cells = <2>;
302 gic_its: msi-controller@e050000 {
303 compatible = "arm,gic-v3-its";
305 msi-controller;
306 #msi-cells = <1>;
309 ppi-partitions {
310 ppi_partition0: interrupt-partition-0 {
314 ppi_partition1: interrupt-partition-1 {
322 compatible = "arm,armv8-timer";
323 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";