Lines Matching +full:bm1880 +full:- +full:clk
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/clock/bm1880-clock.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/reset/bitmain,bm1880-reset.h>
12 compatible = "bitmain,bm1880";
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <1>;
19 #size-cells = <0>;
23 compatible = "arm,cortex-a53";
25 enable-method = "psci";
30 compatible = "arm,cortex-a53";
32 enable-method = "psci";
36 reserved-memory {
37 #address-cells = <2>;
38 #size-cells = <2>;
43 no-map;
48 no-map;
53 no-map;
58 compatible = "arm,psci-0.2";
63 compatible = "arm,armv8-timer";
71 compatible = "fixed-clock";
72 clock-frequency = <25000000>;
73 #clock-cells = <0>;
77 compatible = "simple-bus";
78 #address-cells = <2>;
79 #size-cells = <2>;
82 gic: interrupt-controller@50001000 {
83 compatible = "arm,gic-400";
87 interrupt-controller;
88 #interrupt-cells = <3>;
91 sctrl: system-controller@50010000 {
92 compatible = "bitmain,bm1880-sctrl", "syscon",
93 "simple-mfd";
95 #address-cells = <1>;
96 #size-cells = <1>;
100 compatible = "bitmain,bm1880-pinctrl";
104 clk: clock-controller@e8 {
105 compatible = "bitmain,bm1880-clk";
107 reg-names = "pll", "sys";
109 clock-names = "osc";
110 #clock-cells = <1>;
113 rst: reset-controller@c00 {
114 compatible = "bitmain,bm1880-reset";
116 #reset-cells = <1>;
121 #address-cells = <1>;
122 #size-cells = <0>;
123 compatible = "snps,dw-apb-gpio";
126 porta: gpio-controller@0 {
127 compatible = "snps,dw-apb-gpio-port";
128 gpio-controller;
129 #gpio-cells = <2>;
132 interrupt-controller;
133 #interrupt-cells = <2>;
139 #address-cells = <1>;
140 #size-cells = <0>;
141 compatible = "snps,dw-apb-gpio";
144 portb: gpio-controller@0 {
145 compatible = "snps,dw-apb-gpio-port";
146 gpio-controller;
147 #gpio-cells = <2>;
150 interrupt-controller;
151 #interrupt-cells = <2>;
157 #address-cells = <1>;
158 #size-cells = <0>;
159 compatible = "snps,dw-apb-gpio";
162 portc: gpio-controller@0 {
163 compatible = "snps,dw-apb-gpio-port";
164 gpio-controller;
165 #gpio-cells = <2>;
168 interrupt-controller;
169 #interrupt-cells = <2>;
175 compatible = "snps,dw-apb-uart";
177 clocks = <&clk BM1880_CLK_UART_500M>,
178 <&clk BM1880_CLK_APB_UART>;
179 clock-names = "baudclk", "apb_pclk";
181 reg-shift = <2>;
182 reg-io-width = <4>;
188 compatible = "snps,dw-apb-uart";
190 clocks = <&clk BM1880_CLK_UART_500M>,
191 <&clk BM1880_CLK_APB_UART>;
192 clock-names = "baudclk", "apb_pclk";
194 reg-shift = <2>;
195 reg-io-width = <4>;
201 compatible = "snps,dw-apb-uart";
203 clocks = <&clk BM1880_CLK_UART_500M>,
204 <&clk BM1880_CLK_APB_UART>;
205 clock-names = "baudclk", "apb_pclk";
207 reg-shift = <2>;
208 reg-io-width = <4>;
214 compatible = "snps,dw-apb-uart";
216 clocks = <&clk BM1880_CLK_UART_500M>,
217 <&clk BM1880_CLK_APB_UART>;
218 clock-names = "baudclk", "apb_pclk";
220 reg-shift = <2>;
221 reg-io-width = <4>;