Lines Matching +full:mali +full:- +full:400
1 // SPDX-License-Identifier: GPL-2.0
2 #include "juno-clocks.dtsi"
3 #include "juno-motherboard.dtsi"
11 compatible = "arm,armv7-timer-mem";
13 clock-frequency = <50000000>;
14 #address-cells = <1>;
15 #size-cells = <1>;
19 frame-number = <1>;
31 #mbox-cells = <1>;
33 clock-names = "apb_pclk";
37 compatible = "arm,mmu-400", "arm,smmu-v1";
41 #iommu-cells = <1>;
42 #global-interrupts = <1>;
43 power-domains = <&scpi_devpd 1>;
44 dma-coherent;
49 compatible = "arm,mmu-401", "arm,smmu-v1";
53 #iommu-cells = <1>;
54 #global-interrupts = <1>;
55 dma-coherent;
60 compatible = "arm,mmu-401", "arm,smmu-v1";
64 #iommu-cells = <1>;
65 #global-interrupts = <1>;
66 dma-coherent;
67 power-domains = <&scpi_devpd 0>;
70 gic: interrupt-controller@2c010000 {
71 compatible = "arm,gic-400", "arm,cortex-a15-gic";
76 #address-cells = <1>;
77 #interrupt-cells = <3>;
78 #size-cells = <1>;
79 interrupt-controller;
84 compatible = "arm,gic-v2m-frame";
85 msi-controller;
90 compatible = "arm,gic-v2m-frame";
91 msi-controller;
96 compatible = "arm,gic-v2m-frame";
97 msi-controller;
102 compatible = "arm,gic-v2m-frame";
103 msi-controller;
109 compatible = "arm,armv8-timer";
122 compatible = "arm,coresight-tmc", "arm,primecell";
126 clock-names = "apb_pclk";
127 power-domains = <&scpi_devpd 0>;
129 in-ports {
132 remote-endpoint = <&main_funnel_out_port>;
137 out-ports {
146 compatible = "arm,coresight-tpiu", "arm,primecell";
150 clock-names = "apb_pclk";
151 power-domains = <&scpi_devpd 0>;
152 in-ports {
155 remote-endpoint = <&replicator_out_port0>;
163 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
167 clock-names = "apb_pclk";
168 power-domains = <&scpi_devpd 0>;
170 out-ports {
173 remote-endpoint = <&etf0_in_port>;
178 main_funnel_in_ports: in-ports {
179 #address-cells = <1>;
180 #size-cells = <0>;
185 remote-endpoint = <&cluster0_funnel_out_port>;
192 remote-endpoint = <&cluster1_funnel_out_port>;
199 compatible = "arm,coresight-tmc", "arm,primecell";
204 clock-names = "apb_pclk";
205 power-domains = <&scpi_devpd 0>;
206 arm,scatter-gather;
207 in-ports {
210 remote-endpoint = <&replicator_out_port1>;
217 compatible = "arm,coresight-stm", "arm,primecell";
220 reg-names = "stm-base", "stm-stimulus-base";
223 clock-names = "apb_pclk";
224 power-domains = <&scpi_devpd 0>;
225 out-ports {
234 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
238 clock-names = "apb_pclk";
239 power-domains = <&scpi_devpd 0>;
241 out-ports {
242 #address-cells = <1>;
243 #size-cells = <0>;
249 remote-endpoint = <&tpiu_in_port>;
256 remote-endpoint = <&etr_in_port>;
260 in-ports {
268 cpu_debug0: cpu-debug@22010000 {
269 compatible = "arm,coresight-cpu-debug", "arm,primecell";
273 clock-names = "apb_pclk";
274 power-domains = <&scpi_devpd 0>;
278 compatible = "arm,coresight-etm4x", "arm,primecell";
282 clock-names = "apb_pclk";
283 power-domains = <&scpi_devpd 0>;
284 out-ports {
287 remote-endpoint = <&cluster0_funnel_in_port0>;
294 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
299 clock-names = "apb_pclk";
300 power-domains = <&scpi_devpd 0>;
302 arm,cs-dev-assoc = <&etm0>;
306 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
310 clock-names = "apb_pclk";
311 power-domains = <&scpi_devpd 0>;
312 out-ports {
315 remote-endpoint = <&main_funnel_in_port0>;
320 in-ports {
321 #address-cells = <1>;
322 #size-cells = <0>;
327 remote-endpoint = <&cluster0_etm0_out_port>;
334 remote-endpoint = <&cluster0_etm1_out_port>;
340 cpu_debug1: cpu-debug@22110000 {
341 compatible = "arm,coresight-cpu-debug", "arm,primecell";
345 clock-names = "apb_pclk";
346 power-domains = <&scpi_devpd 0>;
350 compatible = "arm,coresight-etm4x", "arm,primecell";
354 clock-names = "apb_pclk";
355 power-domains = <&scpi_devpd 0>;
356 out-ports {
359 remote-endpoint = <&cluster0_funnel_in_port1>;
366 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
371 clock-names = "apb_pclk";
372 power-domains = <&scpi_devpd 0>;
374 arm,cs-dev-assoc = <&etm1>;
377 cpu_debug2: cpu-debug@23010000 {
378 compatible = "arm,coresight-cpu-debug", "arm,primecell";
382 clock-names = "apb_pclk";
383 power-domains = <&scpi_devpd 0>;
387 compatible = "arm,coresight-etm4x", "arm,primecell";
391 clock-names = "apb_pclk";
392 power-domains = <&scpi_devpd 0>;
393 out-ports {
396 remote-endpoint = <&cluster1_funnel_in_port0>;
403 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
408 clock-names = "apb_pclk";
409 power-domains = <&scpi_devpd 0>;
411 arm,cs-dev-assoc = <&etm2>;
415 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
419 clock-names = "apb_pclk";
420 power-domains = <&scpi_devpd 0>;
421 out-ports {
424 remote-endpoint = <&main_funnel_in_port1>;
429 in-ports {
430 #address-cells = <1>;
431 #size-cells = <0>;
436 remote-endpoint = <&cluster1_etm0_out_port>;
443 remote-endpoint = <&cluster1_etm1_out_port>;
449 remote-endpoint = <&cluster1_etm2_out_port>;
455 remote-endpoint = <&cluster1_etm3_out_port>;
461 cpu_debug3: cpu-debug@23110000 {
462 compatible = "arm,coresight-cpu-debug", "arm,primecell";
466 clock-names = "apb_pclk";
467 power-domains = <&scpi_devpd 0>;
471 compatible = "arm,coresight-etm4x", "arm,primecell";
475 clock-names = "apb_pclk";
476 power-domains = <&scpi_devpd 0>;
477 out-ports {
480 remote-endpoint = <&cluster1_funnel_in_port1>;
487 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
492 clock-names = "apb_pclk";
493 power-domains = <&scpi_devpd 0>;
495 arm,cs-dev-assoc = <&etm3>;
498 cpu_debug4: cpu-debug@23210000 {
499 compatible = "arm,coresight-cpu-debug", "arm,primecell";
503 clock-names = "apb_pclk";
504 power-domains = <&scpi_devpd 0>;
508 compatible = "arm,coresight-etm4x", "arm,primecell";
512 clock-names = "apb_pclk";
513 power-domains = <&scpi_devpd 0>;
514 out-ports {
517 remote-endpoint = <&cluster1_funnel_in_port2>;
524 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
529 clock-names = "apb_pclk";
530 power-domains = <&scpi_devpd 0>;
532 arm,cs-dev-assoc = <&etm4>;
535 cpu_debug5: cpu-debug@23310000 {
536 compatible = "arm,coresight-cpu-debug", "arm,primecell";
540 clock-names = "apb_pclk";
541 power-domains = <&scpi_devpd 0>;
545 compatible = "arm,coresight-etm4x", "arm,primecell";
549 clock-names = "apb_pclk";
550 power-domains = <&scpi_devpd 0>;
551 out-ports {
554 remote-endpoint = <&cluster1_funnel_in_port3>;
561 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
566 clock-names = "apb_pclk";
567 power-domains = <&scpi_devpd 0>;
569 arm,cs-dev-assoc = <&etm5>;
573 compatible = "arm,coresight-cti", "arm,primecell";
577 clock-names = "apb_pclk";
578 power-domains = <&scpi_devpd 0>;
580 #address-cells = <1>;
581 #size-cells = <0>;
583 trig-conns@0 {
585 arm,trig-in-sigs = <2 3>;
586 arm,trig-in-types = <SNK_FULL SNK_ACQCOMP>;
587 arm,trig-out-sigs = <0 1>;
588 arm,trig-out-types = <SNK_FLUSHIN SNK_TRIGIN>;
589 arm,cs-dev-assoc = <&etr_sys>;
592 trig-conns@1 {
594 arm,trig-in-sigs = <0 1>;
595 arm,trig-in-types = <SNK_FULL SNK_ACQCOMP>;
596 arm,trig-out-sigs = <7 6>;
597 arm,trig-out-types = <SNK_FLUSHIN SNK_TRIGIN>;
598 arm,cs-dev-assoc = <&etf_sys0>;
601 trig-conns@2 {
603 arm,trig-in-sigs = <4 5 6 7>;
604 arm,trig-in-types = <STM_TOUT_SPTE STM_TOUT_SW
606 arm,trig-out-sigs = <4 5>;
607 arm,trig-out-types = <STM_HWEVENT STM_HWEVENT>;
608 arm,cs-dev-assoc = <&stm_sys>;
611 trig-conns@3 {
613 arm,trig-out-sigs = <2 3>;
614 arm,trig-out-types = <SNK_FLUSHIN SNK_TRIGIN>;
615 arm,cs-dev-assoc = <&tpiu_sys>;
620 compatible = "arm,coresight-cti", "arm,primecell";
624 clock-names = "apb_pclk";
625 power-domains = <&scpi_devpd 0>;
627 #address-cells = <1>;
628 #size-cells = <0>;
630 trig-conns@0 {
632 arm,trig-in-sigs = <0>;
633 arm,trig-in-types = <GEN_INTREQ>;
634 arm,trig-out-sigs = <0>;
635 arm,trig-out-types = <GEN_HALTREQ>;
636 arm,trig-conn-name = "sys_profiler";
639 trig-conns@1 {
641 arm,trig-out-sigs = <2 3>;
642 arm,trig-out-types = <GEN_HALTREQ GEN_RESTARTREQ>;
643 arm,trig-conn-name = "watchdog";
646 trig-conns@2 {
648 arm,trig-out-sigs = <1 6>;
649 arm,trig-out-types = <GEN_HALTREQ GEN_RESTARTREQ>;
650 arm,trig-conn-name = "g_counter";
655 compatible = "arm,juno-mali", "arm,mali-t624";
660 interrupt-names = "job", "mmu", "gpu";
662 power-domains = <&scpi_devpd 1>;
663 dma-coherent;
664 /* The SMMU is only really of interest to bare-metal hypervisors */
670 compatible = "arm,juno-sram-ns", "mmio-sram";
673 #address-cells = <1>;
674 #size-cells = <1>;
677 cpu_scp_lpri: scp-sram@0 {
678 compatible = "arm,juno-scp-shmem";
682 cpu_scp_hpri: scp-sram@200 {
683 compatible = "arm,juno-scp-shmem";
689 compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic";
692 bus-range = <0 255>;
693 linux,pci-domain = <0>;
694 #address-cells = <3>;
695 #size-cells = <2>;
696 dma-coherent;
701 dma-ranges = <0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x80000000>,
703 #interrupt-cells = <1>;
704 interrupt-map-mask = <0 0 0 7>;
705 interrupt-map = <0 0 0 1 &gic 0 GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
709 msi-parent = <&v2m_0>;
711 iommu-map-mask = <0x0>; /* RC has no means to output PCI RID */
712 iommu-map = <0x0 &smmu_pcie 0x0 0x1>;
721 compatible = "arm,scpi-clocks";
723 scpi_dvfs: clocks-0 {
724 compatible = "arm,scpi-dvfs-clocks";
725 #clock-cells = <1>;
726 clock-indices = <0>, <1>, <2>;
727 clock-output-names = "atlclk", "aplclk","gpuclk";
729 scpi_clk: clocks-1 {
730 compatible = "arm,scpi-variable-clocks";
731 #clock-cells = <1>;
732 clock-indices = <3>;
733 clock-output-names = "pxlclk";
737 scpi_devpd: power-controller {
738 compatible = "arm,scpi-power-domains";
739 num-domains = <2>;
740 #power-domain-cells = <1>;
744 compatible = "arm,scpi-sensors";
745 #thermal-sensor-cells = <1>;
749 thermal-zones {
750 pmic-thermal {
751 polling-delay = <1000>;
752 polling-delay-passive = <100>;
753 thermal-sensors = <&scpi_sensors0 0>;
763 soc-thermal {
764 polling-delay = <1000>;
765 polling-delay-passive = <100>;
766 thermal-sensors = <&scpi_sensors0 3>;
776 big_cluster_thermal_zone: big-cluster-thermal {
777 polling-delay = <1000>;
778 polling-delay-passive = <100>;
779 thermal-sensors = <&scpi_sensors0 21>;
783 little_cluster_thermal_zone: little-cluster-thermal {
784 polling-delay = <1000>;
785 polling-delay-passive = <100>;
786 thermal-sensors = <&scpi_sensors0 22>;
790 gpu0_thermal_zone: gpu0-thermal {
791 polling-delay = <1000>;
792 polling-delay-passive = <100>;
793 thermal-sensors = <&scpi_sensors0 23>;
797 gpu1_thermal_zone: gpu1-thermal {
798 polling-delay = <1000>;
799 polling-delay-passive = <100>;
800 thermal-sensors = <&scpi_sensors0 24>;
806 compatible = "arm,mmu-401", "arm,smmu-v1";
810 #iommu-cells = <1>;
811 #global-interrupts = <1>;
812 dma-coherent;
816 compatible = "arm,mmu-401", "arm,smmu-v1";
820 #iommu-cells = <1>;
821 #global-interrupts = <1>;
825 compatible = "arm,mmu-401", "arm,smmu-v1";
829 #iommu-cells = <1>;
830 #global-interrupts = <1>;
834 compatible = "arm,mmu-401", "arm,smmu-v1";
838 #iommu-cells = <1>;
839 #global-interrupts = <1>;
840 dma-coherent;
843 dma-controller@7ff00000 {
846 #dma-cells = <1>;
866 clock-names = "apb_pclk";
875 clock-names = "pxlclk";
879 remote-endpoint = <&tda998x_1_input>;
890 clock-names = "pxlclk";
894 remote-endpoint = <&tda998x_0_input>;
904 clock-names = "uartclk", "apb_pclk";
908 compatible = "snps,designware-i2c";
910 #address-cells = <1>;
911 #size-cells = <0>;
913 clock-frequency = <400000>;
914 i2c-sda-hold-time-ns = <500>;
917 hdmi-transmitter@70 {
922 remote-endpoint = <&hdlcd0_output>;
927 hdmi-transmitter@71 {
932 remote-endpoint = <&hdlcd1_output>;
939 compatible = "generic-ohci";
947 compatible = "generic-ehci";
954 memory-controller@7ffd0000 {
960 clock-names = "apb_pclk";
971 #interrupt-cells = <1>;
972 interrupt-map-mask = <0 0 15>;
973 interrupt-map = <0 0 0 &gic 0 GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
988 site2: tlx-bus@60000000 {
989 compatible = "simple-bus";
990 #address-cells = <1>;
991 #size-cells = <1>;
993 #interrupt-cells = <1>;
994 interrupt-map-mask = <0 0>;
995 interrupt-map = <0 0 &gic 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;