Lines Matching +full:opp +full:- +full:level
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
16 interrupt-parent = <&aic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
20 clkref: clock-ref {
21 compatible = "fixed-clock";
22 #clock-cells = <0>;
23 clock-frequency = <24000000>;
24 clock-output-names = "clkref";
28 #address-cells = <2>;
29 #size-cells = <0>;
34 cpu-release-addr = <0 0>; /* To be filled in by loader */
35 operating-points-v2 = <&twister_opp>;
36 performance-domains = <&cpufreq>;
37 enable-method = "spin-table";
39 next-level-cache = <&l2_cache>;
40 i-cache-size = <0x10000>;
41 d-cache-size = <0x10000>;
47 cpu-release-addr = <0 0>; /* To be filled in by loader */
48 operating-points-v2 = <&twister_opp>;
49 performance-domains = <&cpufreq>;
50 enable-method = "spin-table";
52 next-level-cache = <&l2_cache>;
53 i-cache-size = <0x10000>;
54 d-cache-size = <0x10000>;
57 l2_cache: l2-cache {
59 cache-level = <2>;
60 cache-unified;
61 cache-size = <0x300000>;
65 twister_opp: opp-table {
66 compatible = "operating-points-v2";
69 opp-hz = /bits/ 64 <300000000>;
70 opp-level = <1>;
71 clock-latency-ns = <800>;
74 opp-hz = /bits/ 64 <396000000>;
75 opp-level = <2>;
76 clock-latency-ns = <53000>;
79 opp-hz = /bits/ 64 <792000000>;
80 opp-level = <3>;
81 clock-latency-ns = <18000>;
84 opp-hz = /bits/ 64 <1080000000>;
85 opp-level = <4>;
86 clock-latency-ns = <21000>;
89 opp-hz = /bits/ 64 <1440000000>;
90 opp-level = <5>;
91 clock-latency-ns = <25000>;
94 opp-hz = /bits/ 64 <1800000000>;
95 opp-level = <6>;
96 clock-latency-ns = <33000>;
99 opp-hz = /bits/ 64 <2160000000>;
100 opp-level = <7>;
101 clock-latency-ns = <45000>;
106 opp-hz = /bits/ 64 <2160000000>;
107 opp-level = <8>;
108 clock-latency-ns = <45000>;
109 turbo-mode;
115 compatible = "simple-bus";
116 #address-cells = <2>;
117 #size-cells = <2>;
118 nonposted-mmio;
121 cpufreq: performance-controller@202220000 {
122 …compatible = "apple,s8000-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
124 #performance-domain-cells = <0>;
128 compatible = "apple,s5l-uart";
130 reg-io-width = <4>;
131 interrupt-parent = <&aic>;
133 /* Use the bootloader-enabled clocks for now. */
135 clock-names = "uart", "clk_uart_baud0";
136 power-domains = <&ps_uart0>;
140 pmgr: power-management@20e000000 {
141 compatible = "apple,s8000-pmgr", "apple,pmgr", "syscon", "simple-mfd";
142 #address-cells = <1>;
143 #size-cells = <1>;
148 aic: interrupt-controller@20e100000 {
149 compatible = "apple,s8000-aic", "apple,aic";
151 #interrupt-cells = <3>;
152 interrupt-controller;
153 power-domains = <&ps_aic>;
157 compatible = "apple,s8000-pinctrl", "apple,pinctrl";
159 power-domains = <&ps_gpio>;
161 gpio-controller;
162 #gpio-cells = <2>;
163 gpio-ranges = <&pinctrl_ap 0 0 219>;
166 interrupt-controller;
167 #interrupt-cells = <2>;
168 interrupt-parent = <&aic>;
179 compatible = "apple,s8000-pinctrl", "apple,pinctrl";
181 power-domains = <&ps_aop_gpio>;
183 gpio-controller;
184 #gpio-cells = <2>;
185 gpio-ranges = <&pinctrl_aop 0 0 28>;
188 interrupt-controller;
189 #interrupt-cells = <2>;
190 interrupt-parent = <&aic>;
200 pmgr_mini: power-management@210200000 {
201 compatible = "apple,s8000-pmgr", "apple,pmgr", "syscon", "simple-mfd";
202 #address-cells = <1>;
203 #size-cells = <1>;
209 compatible = "apple,s8000-wdt", "apple,wdt";
212 interrupt-parent = <&aic>;
218 compatible = "arm,armv8-timer";
219 interrupt-parent = <&aic>;
220 interrupt-names = "phys", "virt";
227 #include "s8001-pmgr.dtsi"