Lines Matching +full:psci +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0
5 #address-cells = <0x1>;
6 #size-cells = <0x0>;
8 cpu-map {
43 CPU0: cpu@0 {
45 compatible = "arm,cortex-a57";
46 reg = <0x0>;
47 enable-method = "psci";
49 i-cache-size = <0xC000>;
50 i-cache-line-size = <64>;
51 i-cache-sets = <256>;
52 d-cache-size = <0x8000>;
53 d-cache-line-size = <64>;
54 d-cache-sets = <256>;
55 l2-cache = <&L2_0>;
61 compatible = "arm,cortex-a57";
62 reg = <0x1>;
63 enable-method = "psci";
65 i-cache-size = <0xC000>;
66 i-cache-line-size = <64>;
67 i-cache-sets = <256>;
68 d-cache-size = <0x8000>;
69 d-cache-line-size = <64>;
70 d-cache-sets = <256>;
71 l2-cache = <&L2_0>;
76 compatible = "arm,cortex-a57";
77 reg = <0x100>;
78 enable-method = "psci";
80 i-cache-size = <0xC000>;
81 i-cache-line-size = <64>;
82 i-cache-sets = <256>;
83 d-cache-size = <0x8000>;
84 d-cache-line-size = <64>;
85 d-cache-sets = <256>;
86 l2-cache = <&L2_1>;
91 compatible = "arm,cortex-a57";
92 reg = <0x101>;
93 enable-method = "psci";
95 i-cache-size = <0xC000>;
96 i-cache-line-size = <64>;
97 i-cache-sets = <256>;
98 d-cache-size = <0x8000>;
99 d-cache-line-size = <64>;
100 d-cache-sets = <256>;
101 l2-cache = <&L2_1>;
106 compatible = "arm,cortex-a57";
107 reg = <0x200>;
108 enable-method = "psci";
110 i-cache-size = <0xC000>;
111 i-cache-line-size = <64>;
112 i-cache-sets = <256>;
113 d-cache-size = <0x8000>;
114 d-cache-line-size = <64>;
115 d-cache-sets = <256>;
116 l2-cache = <&L2_2>;
121 compatible = "arm,cortex-a57";
122 reg = <0x201>;
123 enable-method = "psci";
125 i-cache-size = <0xC000>;
126 i-cache-line-size = <64>;
127 i-cache-sets = <256>;
128 d-cache-size = <0x8000>;
129 d-cache-line-size = <64>;
130 d-cache-sets = <256>;
131 l2-cache = <&L2_2>;
136 compatible = "arm,cortex-a57";
137 reg = <0x300>;
138 enable-method = "psci";
140 i-cache-size = <0xC000>;
141 i-cache-line-size = <64>;
142 i-cache-sets = <256>;
143 d-cache-size = <0x8000>;
144 d-cache-line-size = <64>;
145 d-cache-sets = <256>;
146 l2-cache = <&L2_3>;
151 compatible = "arm,cortex-a57";
152 reg = <0x301>;
153 enable-method = "psci";
155 i-cache-size = <0xC000>;
156 i-cache-line-size = <64>;
157 i-cache-sets = <256>;
158 d-cache-size = <0x8000>;
159 d-cache-line-size = <64>;
160 d-cache-sets = <256>;
161 l2-cache = <&L2_3>;
165 L2_0: l2-cache0 {
166 cache-size = <0x100000>;
167 cache-line-size = <64>;
168 cache-sets = <1024>;
169 cache-unified;
170 next-level-cache = <&L3>;
173 L2_1: l2-cache1 {
174 cache-size = <0x100000>;
175 cache-line-size = <64>;
176 cache-sets = <1024>;
177 cache-unified;
178 next-level-cache = <&L3>;
181 L2_2: l2-cache2 {
182 cache-size = <0x100000>;
183 cache-line-size = <64>;
184 cache-sets = <1024>;
185 cache-unified;
186 next-level-cache = <&L3>;
189 L2_3: l2-cache3 {
190 cache-size = <0x100000>;
191 cache-line-size = <64>;
192 cache-sets = <1024>;
193 cache-unified;
194 next-level-cache = <&L3>;
197 L3: l3-cache {
198 cache-level = <3>;
199 cache-size = <0x800000>;
200 cache-line-size = <64>;
201 cache-sets = <8192>;
202 cache-unified;
206 compatible = "arm,cortex-a57-pmu";
207 interrupts = <0x0 0x7 0x4>,
208 <0x0 0x8 0x4>,
209 <0x0 0x9 0x4>,
210 <0x0 0xa 0x4>,
211 <0x0 0xb 0x4>,
212 <0x0 0xc 0x4>,
213 <0x0 0xd 0x4>,
214 <0x0 0xe 0x4>;
215 interrupt-affinity = <&CPU0>,