Lines Matching +full:0 +full:x250
14 #address-cells = <0>;
15 #size-cells = <0>;
25 reg = <0x0 0x0>;
47 reg = <0xd8140000 0x10000>;
56 reg = <0xD8150000 0x10000>;
62 reg = <0xd8110000 0x10000>;
71 reg = <0xd8130000 0x1000>;
74 #size-cells = <0>;
77 #clock-cells = <0>;
83 #clock-cells = <0>;
89 #clock-cells = <0>;
92 reg = <0x200>;
96 #clock-cells = <0>;
99 reg = <0x204>;
103 #clock-cells = <0>;
106 reg = <0x208>;
110 #clock-cells = <0>;
113 reg = <0x20c>;
117 #clock-cells = <0>;
120 divisor-reg = <0x300>;
124 #clock-cells = <0>;
127 divisor-reg = <0x304>;
131 #clock-cells = <0>;
134 divisor-reg = <0x350>;
138 #clock-cells = <0>;
141 divisor-reg = <0x310>;
145 #clock-cells = <0>;
148 enable-reg = <0x250>;
153 #clock-cells = <0>;
156 enable-reg = <0x250>;
161 #clock-cells = <0>;
164 enable-reg = <0x250>;
169 #clock-cells = <0>;
172 enable-reg = <0x250>;
177 #clock-cells = <0>;
180 enable-reg = <0x250>;
185 #clock-cells = <0>;
188 enable-reg = <0x250>;
193 #clock-cells = <0>;
196 divisor-reg = <0x328>;
197 divisor-mask = <0x3f>;
198 enable-reg = <0x254>;
206 reg = <0xd8130100 0x28>;
212 reg = <0xd8007100 0x200>;
218 reg = <0xd8007300 0x200>;
219 interrupts = <0>;
224 reg = <0xd8050800 0x200>;
229 reg = <0xd8050400 0x100>;
234 reg = <0xd8200000 0x1040>;
242 reg = <0xd82b0000 0x1040>;
250 reg = <0xd8210000 0x1040>;
258 reg = <0xd82c0000 0x1040>;
266 reg = <0xd8370000 0x1040>;
274 reg = <0xd8380000 0x1040>;
282 reg = <0xd8100000 0x10000>;
288 reg = <0xd800a000 0x400>;