Lines Matching +full:0 +full:x3700
27 #size-cells = <0>;
28 cpu@0 {
31 reg = <0>;
61 reg = <0x44000000 0x10000>;
69 reg = <0x48180000 0x4000>;
72 ranges = <0 0x48180000 0x4000>;
76 #size-cells = <0>;
85 reg = <0x48140000 0x21000>;
89 ranges = <0 0x48140000 0x21000>;
93 reg = <0x800 0x50a>;
95 #size-cells = <0>;
98 pinctrl-single,function-mask = <0xf>;
104 reg = <0x600 0x110>;
107 ranges = <0 0x600 0x110>;
111 reg = <0x20 0x8>;
115 #phy-cells = <0>;
121 reg = <0x28 0x8>;
125 #phy-cells = <0>;
132 #size-cells = <0>;
141 reg = <0x49000000 0x4>;
143 clocks = <&alwon_clkctrl DM816_TPCC_CLKCTRL 0>;
147 ranges = <0x0 0x49000000 0x10000>;
149 edma: dma@0 {
151 reg = <0 0x10000>;
160 <&edma_tptc2 3>, <&edma_tptc3 0>;
168 reg = <0x49800000 0x4>,
169 <0x49800010 0x4>;
175 clocks = <&alwon_clkctrl DM816_TPTC0_CLKCTRL 0>;
179 ranges = <0x0 0x49800000 0x100000>;
181 edma_tptc0: dma@0 {
183 reg = <0 0x100000>;
191 reg = <0x49900000 0x4>,
192 <0x49900010 0x4>;
198 clocks = <&alwon_clkctrl DM816_TPTC1_CLKCTRL 0>;
202 ranges = <0x0 0x49900000 0x100000>;
204 edma_tptc1: dma@0 {
206 reg = <0 0x100000>;
214 reg = <0x49a00000 0x4>,
215 <0x49a00010 0x4>;
221 clocks = <&alwon_clkctrl DM816_TPTC2_CLKCTRL 0>;
225 ranges = <0x0 0x49a00000 0x100000>;
227 edma_tptc2: dma@0 {
229 reg = <0 0x100000>;
237 reg = <0x49b00000 0x4>,
238 <0x49b00010 0x4>;
244 clocks = <&alwon_clkctrl DM816_TPTC3_CLKCTRL 0>;
248 ranges = <0x0 0x49b00000 0x100000>;
250 edma_tptc3: dma@0 {
252 reg = <0 0x100000>;
261 reg = <0x48080000 0x2000>;
269 reg = <0x48032000 0x1000>;
281 reg = <0x4804c000 0x1000>;
292 reg = <0x50000000 0x2000>;
296 dmas = <&edma 52 0>;
309 reg = <0x48028000 0x1000>;
311 #size-cells = <0>;
318 reg = <0x4802a000 0x1000>;
320 #size-cells = <0>;
328 reg = <0x48200000 0x1000>;
333 reg = <0x480c0000 0x1000>;
340 reg = <0x480c8000 0x2000>;
347 ti,mbox-tx = <3 0 0>;
348 ti,mbox-rx = <0 0 0>;
354 reg = <0x480ca000 0x2000>;
362 #size-cells = <0>;
363 reg = <0x4a100800 0x100>;
366 phy0: ethernet-phy@0 {
377 reg = <0x4a100000 0x800
378 0x4a100900 0x3700>;
381 ti,davinci-ctrl-reg-offset = <0>;
382 ti,davinci-ctrl-mod-reg-offset = <0x900>;
383 ti,davinci-ctrl-ram-offset = <0x2000>;
384 ti,davinci-ctrl-ram-size = <0x2000>;
392 reg = <0x4a120000 0x4000>;
395 ti,davinci-ctrl-reg-offset = <0>;
396 ti,davinci-ctrl-mod-reg-offset = <0x900>;
397 ti,davinci-ctrl-ram-offset = <0x2000>;
398 ti,davinci-ctrl-ram-size = <0x2000>;
405 reg = <0x4a140000 0x10000>;
412 reg = <0x48030000 0x1000>;
414 #size-cells = <0>;
418 dmas = <&edma 16 0 &edma 17 0
419 &edma 18 0 &edma 19 0
420 &edma 20 0 &edma 21 0
421 &edma 22 0 &edma 23 0>;
428 reg = <0x48060000 0x11000>;
431 dmas = <&edma 24 0 &edma 25 0>;
437 reg = <0x4802e000 0x4>,
438 <0x4802e010 0x4>;
445 clocks = <&alwon_clkctrl DM816_TIMER1_CLKCTRL 0>;
449 ranges = <0x0 0x4802e000 0x1000>;
451 timer1: timer@0 {
453 reg = <0 0x1000>;
456 clocks = <&alwon_clkctrl DM816_TIMER1_CLKCTRL 0>;
463 reg = <0x48040000 0x4>,
464 <0x48040010 0x4>;
471 clocks = <&alwon_clkctrl DM816_TIMER2_CLKCTRL 0>;
475 ranges = <0x0 0x48040000 0x1000>;
477 timer2: timer@0 {
479 reg = <0 0x1000>;
481 clocks = <&alwon_clkctrl DM816_TIMER2_CLKCTRL 0>;
488 reg = <0x48042000 0x2000>;
495 reg = <0x48044000 0x2000>;
503 reg = <0x48046000 0x2000>;
511 reg = <0x48048000 0x2000>;
519 reg = <0x4804a000 0x2000>;
528 reg = <0x48020000 0x2000>;
531 dmas = <&edma 26 0 &edma 27 0>;
538 reg = <0x48022000 0x2000>;
541 dmas = <&edma 28 0 &edma 29 0>;
548 reg = <0x48024000 0x2000>;
551 dmas = <&edma 30 0 &edma 31 0>;
558 reg = <0x47401000 0x400000>;
566 reg = <0x47401400 0x400
567 0x47401000 0x200>;
572 interface-type = <0>;
580 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
581 &cppi41dma 2 0 &cppi41dma 3 0
582 &cppi41dma 4 0 &cppi41dma 5 0
583 &cppi41dma 6 0 &cppi41dma 7 0
584 &cppi41dma 8 0 &cppi41dma 9 0
585 &cppi41dma 10 0 &cppi41dma 11 0
586 &cppi41dma 12 0 &cppi41dma 13 0
587 &cppi41dma 14 0 &cppi41dma 0 1
606 reg = <0x47401c00 0x400
607 0x47401800 0x200>;
612 interface-type = <0>;
620 dmas = <&cppi41dma 15 0 &cppi41dma 16 0
621 &cppi41dma 17 0 &cppi41dma 18 0
622 &cppi41dma 19 0 &cppi41dma 20 0
623 &cppi41dma 21 0 &cppi41dma 22 0
624 &cppi41dma 23 0 &cppi41dma 24 0
625 &cppi41dma 25 0 &cppi41dma 26 0
626 &cppi41dma 27 0 &cppi41dma 28 0
627 &cppi41dma 29 0 &cppi41dma 15 1
646 reg = <0x47400000 0x1000
647 0x47402000 0x1000
648 0x47403000 0x1000
649 0x47404000 0x4000>;
665 reg = <0x480c2000 0x1000>;
666 interrupts = <0>;
677 timer@0 {
687 timer@0 {