Lines Matching +full:arm +full:- +full:io
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/soc/rockchip,boot-mode.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 interrupt-parent = <&gic>;
37 compatible = "fixed-clock";
38 clock-frequency = <24000000>;
39 #clock-cells = <0>;
40 clock-output-names = "xin24m";
44 compatible = "arm,mali-400";
47 clock-names = "bus", "core";
48 assigned-clocks = <&cru ACLK_GPU>;
49 assigned-clock-rates = <100000000>;
54 vpu: video-codec@10104000 {
55 compatible = "rockchip,rk3066-vpu";
59 interrupt-names = "vepu", "vdpu";
62 clock-names = "aclk_vdpu", "hclk_vdpu",
66 L2: cache-controller@10138000 {
67 compatible = "arm,pl310-cache";
69 cache-unified;
70 cache-level = <2>;
74 compatible = "arm,cortex-a9-scu";
78 global_timer: global-timer@1013c200 {
79 compatible = "arm,cortex-a9-global-timer";
92 local_timer: local-timer@1013c600 {
93 compatible = "arm,cortex-a9-twd-timer";
99 gic: interrupt-controller@1013d000 {
100 compatible = "arm,cortex-a9-gic";
101 interrupt-controller;
102 #interrupt-cells = <3>;
108 compatible = "snps,dw-apb-uart";
111 reg-shift = <2>;
112 reg-io-width = <1>;
113 clock-names = "baudclk", "apb_pclk";
119 compatible = "snps,dw-apb-uart";
122 reg-shift = <2>;
123 reg-io-width = <1>;
124 clock-names = "baudclk", "apb_pclk";
130 compatible = "rockchip,rk3066-qos", "syscon";
135 compatible = "rockchip,rk3066-qos", "syscon";
140 compatible = "rockchip,rk3066-qos", "syscon";
145 compatible = "rockchip,rk3066-qos", "syscon";
150 compatible = "rockchip,rk3066-qos", "syscon";
155 compatible = "rockchip,rk3066-qos", "syscon";
160 compatible = "rockchip,rk3066-qos", "syscon";
165 compatible = "rockchip,rk3066-qos", "syscon";
170 compatible = "rockchip,rk3066-usb", "snps,dwc2";
174 clock-names = "otg";
176 g-np-tx-fifo-size = <16>;
177 g-rx-fifo-size = <275>;
178 g-tx-fifo-size = <256 128 128 64 64 32>;
180 phy-names = "usb2-phy";
189 clock-names = "otg";
192 phy-names = "usb2-phy";
197 compatible = "snps,arc-emac";
204 clock-names = "hclk", "macref";
205 max-speed = <100>;
206 phy-mode = "rmii";
212 compatible = "rockchip,rk2928-dw-mshc";
216 clock-names = "biu", "ciu";
218 dma-names = "rx-tx";
219 fifo-depth = <256>;
221 reset-names = "reset";
226 compatible = "rockchip,rk2928-dw-mshc";
230 clock-names = "biu", "ciu";
232 dma-names = "rx-tx";
233 fifo-depth = <256>;
235 reset-names = "reset";
240 compatible = "rockchip,rk2928-dw-mshc";
244 clock-names = "biu", "ciu";
246 dma-names = "rx-tx";
247 fifo-depth = <256>;
249 reset-names = "reset";
253 nfc: nand-controller@10500000 {
254 compatible = "rockchip,rk2928-nfc";
258 clock-names = "ahb";
263 compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd";
266 reboot-mode {
267 compatible = "syscon-reboot-mode";
269 mode-normal = <BOOT_NORMAL>;
270 mode-recovery = <BOOT_RECOVERY>;
271 mode-bootloader = <BOOT_FASTBOOT>;
272 mode-loader = <BOOT_BL_DOWNLOAD>;
277 compatible = "syscon", "simple-mfd";
281 dmac1_s: dma-controller@20018000 {
282 compatible = "arm,pl330", "arm,primecell";
286 #dma-cells = <1>;
287 arm,pl330-broken-no-flushp;
288 arm,pl330-periph-burst;
290 clock-names = "apb_pclk";
293 dmac1_ns: dma-controller@2001c000 {
294 compatible = "arm,pl330", "arm,primecell";
298 #dma-cells = <1>;
299 arm,pl330-broken-no-flushp;
300 arm,pl330-periph-burst;
302 clock-names = "apb_pclk";
307 compatible = "rockchip,rk3066-i2c";
310 #address-cells = <1>;
311 #size-cells = <0>;
315 clock-names = "i2c";
322 compatible = "rockchip,rk3066-i2c";
325 #address-cells = <1>;
326 #size-cells = <0>;
331 clock-names = "i2c";
337 compatible = "rockchip,rk2928-pwm";
339 #pwm-cells = <2>;
345 compatible = "rockchip,rk2928-pwm";
347 #pwm-cells = <2>;
353 compatible = "snps,dw-wdt";
361 compatible = "rockchip,rk2928-pwm";
363 #pwm-cells = <2>;
369 compatible = "rockchip,rk2928-pwm";
371 #pwm-cells = <2>;
377 compatible = "rockchip,rk3066-i2c";
380 #address-cells = <1>;
381 #size-cells = <0>;
386 clock-names = "i2c";
392 compatible = "rockchip,rk3066-i2c";
395 #address-cells = <1>;
396 #size-cells = <0>;
401 clock-names = "i2c";
407 compatible = "rockchip,rk3066-i2c";
410 #address-cells = <1>;
411 #size-cells = <0>;
416 clock-names = "i2c";
422 compatible = "snps,dw-apb-uart";
425 reg-shift = <2>;
426 reg-io-width = <1>;
427 clock-names = "baudclk", "apb_pclk";
433 compatible = "snps,dw-apb-uart";
436 reg-shift = <2>;
437 reg-io-width = <1>;
438 clock-names = "baudclk", "apb_pclk";
447 #io-channel-cells = <1>;
449 clock-names = "saradc", "apb_pclk";
451 reset-names = "saradc-apb";
456 compatible = "rockchip,rk3066-spi";
458 clock-names = "spiclk", "apb_pclk";
461 #address-cells = <1>;
462 #size-cells = <0>;
464 dma-names = "tx", "rx";
469 compatible = "rockchip,rk3066-spi";
471 clock-names = "spiclk", "apb_pclk";
474 #address-cells = <1>;
475 #size-cells = <0>;
477 dma-names = "tx", "rx";
481 dmac2: dma-controller@20078000 {
482 compatible = "arm,pl330", "arm,primecell";
486 #dma-cells = <1>;
487 arm,pl330-broken-no-flushp;
488 arm,pl330-periph-burst;
490 clock-names = "apb_pclk";