Lines Matching +full:0 +full:x100a0000
44 #size-cells = <0>;
50 reg = <0xf00>;
61 reg = <0xf01>;
69 reg = <0xf02>;
77 reg = <0xf03>;
83 cpu_opp_table: opp-table-0 {
153 #clock-cells = <0>;
158 reg = <0x10080000 0x2000>;
161 ranges = <0 0x10080000 0x2000>;
163 smp-sram@0 {
165 reg = <0x00 0x10>;
171 reg = <0x10090000 0x10000>;
194 reg = <0x100a0000 0x1000>;
200 #size-cells = <0>;
226 #power-domain-cells = <0>;
237 #power-domain-cells = <0>;
244 #power-domain-cells = <0>;
251 reg = <0x1012d000 0x20>;
256 reg = <0x1012e000 0x20>;
261 reg = <0x1012f000 0x20>;
266 reg = <0x1012f080 0x20>;
271 reg = <0x1012f100 0x20>;
276 reg = <0x1012f180 0x20>;
281 reg = <0x1012f200 0x20>;
286 reg = <0x10139000 0x1000>,
287 <0x1013a000 0x1000>,
288 <0x1013c000 0x2000>,
289 <0x1013e000 0x2000>;
293 #address-cells = <0>;
298 reg = <0x10180000 0x40000>;
313 reg = <0x101c0000 0x20000>;
323 reg = <0x101e0000 0x20000>;
333 reg = <0x10214000 0x4000>;
349 reg = <0x10218000 0x4000>;
365 reg = <0x1021c000 0x4000>;
381 reg = <0x10500000 0x4000>;
386 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0
393 reg = <0x20000000 0x1000>;
405 reg = <0x20008000 0x1000>;
411 reg = <0x017c 0x0c>;
417 #clock-cells = <0>;
423 #phy-cells = <0>;
433 #phy-cells = <0>;
441 reg = <0x20044000 0x20>;
449 reg = <0x20044020 0x20>;
457 reg = <0x20044040 0x20>;
465 reg = <0x20044060 0x20>;
473 reg = <0x20044080 0x20>;
481 reg = <0x200440a0 0x20>;
489 reg = <0x2004c000 0x100>;
497 reg = <0x20050000 0x10>;
500 pinctrl-0 = <&pwm0_pin>;
507 reg = <0x20050010 0x10>;
510 pinctrl-0 = <&pwm1_pin>;
517 reg = <0x20050020 0x10>;
520 pinctrl-0 = <&pwm2_pin>;
527 reg = <0x20050030 0x10>;
530 pinctrl-0 = <&pwm3_pin>;
537 reg = <0x20056000 0x1000>;
542 pinctrl-0 = <&i2c1_xfer>;
544 #size-cells = <0>;
550 reg = <0x2005a000 0x1000>;
555 pinctrl-0 = <&i2c2_xfer>;
557 #size-cells = <0>;
563 reg = <0x2005e000 0x1000>;
568 pinctrl-0 = <&i2c3_xfer>;
570 #size-cells = <0>;
576 reg = <0x20060000 0x100>;
584 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
592 reg = <0x20064000 0x100>;
600 pinctrl-0 = <&uart1_xfer>;
608 reg = <0x20068000 0x100>;
616 pinctrl-0 = <&uart2_xfer>;
624 reg = <0x2006c000 0x100>;
636 reg = <0x20072000 0x1000>;
641 pinctrl-0 = <&i2c0_xfer>;
643 #size-cells = <0>;
649 reg = <0x20074000 0x1000>;
656 pinctrl-0 = <&spi0_tx &spi0_rx &spi0_clk &spi0_cs0 &spi0_cs1>;
658 #size-cells = <0>;
664 reg = <0x20078000 0x4000>;
665 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
676 reg = <0x2008c000 0x4000>;
697 #address-cells = <0x1>;
698 #size-cells = <0x0>;
711 reg = <0x2007c000 0x100>;
722 reg = <0x20080000 0x100>;
733 reg = <0x20084000 0x100>;
744 reg = <0x20088000 0x100>;
836 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>,
837 <0 RK_PA7 2 &pcfg_pull_none>;
841 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>;
845 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
851 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
852 <0 RK_PA1 1 &pcfg_pull_none>;
858 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
859 <0 RK_PA3 1 &pcfg_pull_none>;
872 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
873 <0 RK_PA7 1 &pcfg_pull_none>;
879 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>,
880 <0 RK_PB1 1 &pcfg_pull_none>,
881 <0 RK_PB3 1 &pcfg_pull_none>,
882 <0 RK_PB4 1 &pcfg_pull_none>,
883 <0 RK_PB5 1 &pcfg_pull_none>,
884 <0 RK_PB6 1 &pcfg_pull_none>;
975 rockchip,pins = <0 RK_PD2 1 &pcfg_pull_none>;
981 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
987 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>;
1003 rockchip,pins = <0 RK_PA3 2 &pcfg_pull_default>;
1007 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_default>;
1095 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_default>;
1099 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_default>;
1103 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_default>;
1107 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_default>;
1122 rockchip,pins = <0 RK_PC1 2 &pcfg_pull_none>;
1148 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>;
1152 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>;