Lines Matching +full:0 +full:xfa00000
21 reg = <0xfa00000 0x200000>;
28 #size-cells = <0>;
30 cpu@0 {
33 reg = <0>;
94 reg = <0x0 0x0>;
189 interrupts = <GIC_PPI 7 0xf04>;
195 #clock-cells = <0>;
201 #clock-cells = <0>;
208 interrupts = <GIC_PPI 2 0xf08>,
209 <GIC_PPI 3 0xf08>,
210 <GIC_PPI 4 0xf08>,
211 <GIC_PPI 1 0xf08>;
234 reg = <0xf9000000 0x1000>,
235 <0xf9002000 0x1000>;
240 reg = <0xf9011000 0x1000>;
245 reg = <0xfc190000 0x10000>;
250 reg = <0xfc4bc000 0x1000>;
255 reg = <0xd0 0x1>;
256 bits = <0 8>;
260 reg = <0xd1 0x1>;
261 bits = <0 6>;
265 reg = <0xd1 0x2>;
270 reg = <0xd2 0x2>;
275 reg = <0xd3 0x1>;
280 reg = <0xd4 0x1>;
281 bits = <0 6>;
285 reg = <0xd4 0x2>;
290 reg = <0xd5 0x2>;
295 reg = <0xd6 0x1>;
300 reg = <0xd7 0x1>;
301 bits = <0 6>;
305 reg = <0xd7 0x1>;
310 reg = <0xd8 0x1>;
311 bits = <0 6>;
315 reg = <0xd8 0x2>;
320 reg = <0xd9 0x2>;
325 reg = <0xda 0x2>;
330 reg = <0xdb 0x1>;
335 reg = <0xdc 0x1>;
336 bits = <0 6>;
340 reg = <0xdc 0x2>;
345 reg = <0xdd 0x2>;
350 reg = <0xde 0x2>;
355 reg = <0xdf 0x1>;
356 bits = <0 6>;
360 reg = <0xe0 0x1>;
361 bits = <0 6>;
365 reg = <0xe0 0x2>;
370 reg = <0xe1 0x2>;
375 reg = <0xe2 0x2>;
380 reg = <0xe3 0x2>;
381 bits = <0 6>;
385 reg = <0xe3 0x1>;
390 reg = <0xe4 0x1>;
391 bits = <0 6>;
395 reg = <0xe4 0x2>;
400 reg = <0xe5 0x2>;
405 reg = <0xe6 0x2>;
410 reg = <0xe7 0x1>;
411 bits = <0 6>;
415 reg = <0x440 0x1>;
416 bits = <0 8>;
420 reg = <0x441 0x1>;
421 bits = <0 6>;
425 reg = <0x441 0x2>;
430 reg = <0x442 0x2>;
435 reg = <0x443 0x1>;
440 reg = <0x444 0x1>;
441 bits = <0 6>;
445 reg = <0x444 0x2>;
450 reg = <0x445 0x2>;
455 reg = <0x446 0x1>;
460 reg = <0x447 0x1>;
465 reg = <0x448 0x1>;
466 bits = <0 6>;
470 reg = <0x448 0x2>;
475 reg = <0x449 0x2>;
480 reg = <0x44a 0x2>;
485 reg = <0x44b 0x3>;
490 reg = <0x44c 0x1>;
491 bits = <0 6>;
495 reg = <0x44c 0x2>;
500 reg = <0x44d 0x2>;
505 reg = <0x44e 0x1>;
512 reg = <0xfc4a9000 0x1000>, /* TM */
513 <0xfc4a8000 0x1000>; /* SROT */
578 reg = <0xf9020000 0x1000>;
582 frame-number = <0>;
585 reg = <0xf9021000 0x1000>,
586 <0xf9022000 0x1000>;
592 reg = <0xf9023000 0x1000>;
599 reg = <0xf9024000 0x1000>;
606 reg = <0xf9025000 0x1000>;
613 reg = <0xf9026000 0x1000>;
620 reg = <0xf9027000 0x1000>;
627 reg = <0xf9028000 0x1000>;
634 reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
639 reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
644 reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
649 reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
654 reg = <0xf9012000 0x1000>;
660 reg = <0xf9088000 0x1000>,
661 <0xf9008000 0x1000>;
666 reg = <0xf9098000 0x1000>,
667 <0xf9008000 0x1000>;
672 reg = <0xf90a8000 0x1000>,
673 <0xf9008000 0x1000>;
678 reg = <0xf90b8000 0x1000>,
679 <0xf9008000 0x1000>;
684 reg = <0xfc4ab000 0x4>;
692 reg = <0xfc400000 0x4000>;
695 <0>, /* ufs */
696 <0>,
697 <0>,
698 <0>,
699 <0>, /* sata */
700 <0>,
701 <0>; /* pcie */
715 reg = <0xfd484000 0x1000>;
721 reg = <0xfc428000 0x4000>;
726 reg = <0xfd510000 0x4000>;
728 gpio-ranges = <&tlmm 0 0 147>;
737 reg = <0xf995e000 0x1000>;
746 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
759 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
773 reg = <0xfc4cf000 0x1000>,
774 <0xfc4cb000 0x1000>,
775 <0xfc4ca000 0x1000>;
778 qcom,ee = <0>;
779 qcom,channel = <0>;
781 #size-cells = <0>;
792 qcom,ipc = <&apcs 8 0>;
799 regulators-0 {