Lines Matching +full:tegra30 +full:- +full:i2c
1 // SPDX-License-Identifier: GPL-2.0
2 #include "tegra30.dtsi"
15 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
16 nvidia,hpd-gpio =
18 pll-supply = <®_1v8_avdd_hdmi_pll>;
19 vdd-supply = <®_3v3_avdd_hdmi>;
24 lan-reset-n-hog {
25 gpio-hog;
27 output-high;
28 line-name = "LAN_RESET#";
33 pinctrl-names = "default";
34 pinctrl-0 = <&state_default>;
37 /* Analogue Audio (On-module) */
38 clk1-out-pw4 {
43 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
45 dap3-fs-pp0 {
56 gmi-ad0-pg0 {
100 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
103 dap4-din-pp5 {
120 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
122 lcd-d18-pm2 {
134 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
136 lcd-cs0-n-pn4 {
151 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
153 lcd-pwr0-pb2 {
161 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
170 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
173 lcd-cs1-n-pw0 {
178 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
186 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
188 /* Tri-stating GMI_WR_N on nPWE SODIMM pin 99 */
189 sdmmc3-dat4-pd1 {
194 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
196 /* Not tri-stating GMI_WR_N on RDnWR SODIMM pin 93 */
197 sdmmc3-dat5-pd0 {
202 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
214 sdmmc3-dat3-pb4 {
222 kb-row8-ps0 {
227 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
231 ddc-scl-pv4 {
237 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
241 gen2-i2c-scl-pt5 {
245 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
248 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
250 spdif-in-pk6 {
255 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
259 clk2-out-pw5 {
267 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
269 lcd-pwr1-pc1 {
276 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
285 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
289 hdmi-int-pn7 {
294 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
297 /* Colibri I2C */
298 gen1-i2c-scl-pc4 {
304 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
305 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
309 lcd-d0-pe0 {
335 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
341 lcd-m1-pw1 {
346 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
350 kb-row10-ps2 {
356 kb-row11-ps3 {
367 gmi-wp-n-pc7 {
372 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
375 cam-mclk-pcc0 {
380 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
382 cam-i2c-scl-pbb1 {
388 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
389 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
397 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
404 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
408 gmi-rst-n-pi4 {
419 vi-vsync-pd6 {
439 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
443 sdmmc3-dat2-pb5 {
451 sdmmc3-clk-pa6 {
459 sdmmc3-cmd-pa7 {
467 ulpi-clk-py0 {
477 sdmmc3-dat6-pd3 {
483 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
486 /* Colibri UART-A */
487 ulpi-data0 {
501 /* Colibri UART-B */
502 gmi-a16-pj7 {
512 /* Colibri UART-C */
513 uart2-rxd {
522 spdif-out-pk5 {
527 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
531 spi2-cs1-n-pw2 {
539 spi2-cs2-n-pw3 {
544 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
548 crt-hsync-pv6 {
554 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
557 /* eMMC (On-module) */
558 sdmmc4-clk-pcc4 {
565 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
567 sdmmc4-dat0-paa0 {
579 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
582 /* LAN_EXT_WAKEUP#, LAN_PME (On-module) */
583 pex-l0-rst-n-pdd1 {
589 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
591 /* LAN_V_BUS, LAN_RESET# (On-module) */
592 pex-l0-clkreq-n-pdd2 {
598 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
602 pex-l2-rst-n-pcc6 {
608 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
612 clk1-req-pee2 {
618 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
620 clk2-req-pcc5 {
630 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
632 gmi-dqs-pi2 {
642 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
644 kb-col0-pq0 {
656 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
658 kb-row0-pr0 {
666 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
668 lcd-pwr2-pc6 {
673 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
676 /* Power I2C (On-module) */
677 pwr-i2c-scl-pz6 {
683 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
684 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
688 * THERMD_ALERT#, unlatched I2C address pin of LM95245
692 lcd-dc1-pd2 {
697 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
700 /* TOUCH_PEN_INT# (On-module) */
706 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
712 compatible = "nvidia,tegra30-hsuart";
713 reset-names = "serial";
714 /delete-property/ reg-shift;
718 compatible = "nvidia,tegra30-hsuart";
719 reset-names = "serial";
720 /delete-property/ reg-shift;
723 hdmi_ddc: i2c@7000c700 {
724 clock-frequency = <10000>;
728 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
729 * touch screen controller (On-module)
731 i2c@7000d000 {
733 clock-frequency = <100000>;
739 #sound-dai-cells = <0>;
740 VDDA-supply = <®_module_3v3_audio>;
741 VDDD-supply = <®_1v8_vio>;
742 VDDIO-supply = <®_module_3v3>;
751 #interrupt-cells = <2>;
752 interrupt-controller;
753 wakeup-source;
755 ti,system-power-controller;
757 #gpio-cells = <2>;
758 gpio-controller;
760 vcc1-supply = <®_module_3v3>;
761 vcc2-supply = <®_module_3v3>;
762 vcc3-supply = <®_1v8_vio>;
763 vcc4-supply = <®_module_3v3>;
764 vcc5-supply = <®_module_3v3>;
765 vcc6-supply = <®_1v8_vio>;
766 vcc7-supply = <®_5v0_charge_pump>;
767 vccio-supply = <®_module_3v3>;
771 regulator-name = "+V1.35_VDDIO_DDR";
772 regulator-min-microvolt = <1350000>;
773 regulator-max-microvolt = <1350000>;
774 regulator-always-on;
780 regulator-name = "+V1.0_VDD_CPU";
781 regulator-min-microvolt = <800000>;
782 regulator-max-microvolt = <1250000>;
783 regulator-coupled-with = <&vdd_core>;
784 regulator-coupled-max-spread = <300000>;
785 regulator-max-step-microvolt = <100000>;
786 regulator-always-on;
788 nvidia,tegra-cpu-regulator;
792 regulator-name = "+V1.8";
793 regulator-min-microvolt = <1800000>;
794 regulator-max-microvolt = <1800000>;
795 regulator-always-on;
806 regulator-name = "EN_+V3.3";
807 regulator-min-microvolt = <3300000>;
808 regulator-max-microvolt = <3300000>;
809 regulator-always-on;
815 regulator-name = "+V1.2_VDD_RTC";
816 regulator-min-microvolt = <1200000>;
817 regulator-max-microvolt = <1200000>;
818 regulator-always-on;
826 regulator-name = "+V2.8_AVDD_VDAC";
827 regulator-min-microvolt = <2800000>;
828 regulator-max-microvolt = <2800000>;
829 regulator-always-on;
838 regulator-name = "+V1.05_AVDD_PLLE";
839 regulator-min-microvolt = <1100000>;
840 regulator-max-microvolt = <1100000>;
844 regulator-name = "+V1.2_AVDD_PLL";
845 regulator-min-microvolt = <1200000>;
846 regulator-max-microvolt = <1200000>;
847 regulator-always-on;
851 regulator-name = "+V1.0_VDD_DDR_HS";
852 regulator-min-microvolt = <1000000>;
853 regulator-max-microvolt = <1000000>;
854 regulator-always-on;
863 irq-gpio = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
866 irq-trigger = <0x1>;
868 st,adc-freq = <1>;
869 /* 12-bit ADC */
870 st,mod-12b = <1>;
872 st,ref-sel = <0>;
874 st,sample-time = <4>;
875 /* forbid to use ADC channels 3-0 (touch) */
878 compatible = "st,stmpe-adc";
879 st,norequest-mask = <0x0F>;
883 compatible = "st,stmpe-ts";
885 st,ave-ctrl = <3>;
887 st,fraction-z = <7>;
892 st,i-drive = <1>;
896 st,touch-det-delay = <5>;
904 temp-sensor@4c {
914 regulator-name = "tps62362-vout";
915 regulator-min-microvolt = <900000>;
916 regulator-max-microvolt = <1400000>;
917 regulator-coupled-with = <&vddctrl_reg>;
918 regulator-coupled-max-spread = <300000>;
919 regulator-max-step-microvolt = <100000>;
920 regulator-boot-on;
921 regulator-always-on;
923 nvidia,tegra-core-regulator;
928 nvidia,invert-interrupt;
929 nvidia,suspend-mode = <1>;
930 nvidia,cpu-pwr-good-time = <5000>;
931 nvidia,cpu-pwr-off-time = <5000>;
932 nvidia,core-pwr-good-time = <3845 3845>;
933 nvidia,core-pwr-off-time = <0>;
934 nvidia,core-power-req-active-high;
935 nvidia,sys-clock-req-active-high;
936 core-supply = <&vdd_core>;
939 i2c-thermtrip {
940 nvidia,i2c-controller-id = <4>;
941 nvidia,bus-addr = <0x2d>;
942 nvidia,reg-addr = <0x3f>;
943 nvidia,reg-data = <0x1>;
960 bus-width = <8>;
961 non-removable;
962 vmmc-supply = <®_module_3v3>; /* VCC */
963 vqmmc-supply = <®_1v8_vio>; /* VCCQ */
964 mmc-ddr-1_8v;
967 /* EHCI instance 1: USB2_DP/N -> AX88772B (On-module) */
970 #address-cells = <1>;
971 #size-cells = <0>;
976 local-mac-address = [00 00 00 00 00 00];
980 usb-phy@7d004000 {
982 vbus-supply = <®_lan_v_bus>;
985 clk32k_in: clock-xtal1 {
986 compatible = "fixed-clock";
987 #clock-cells = <0>;
988 clock-frequency = <32768>;
991 reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll {
992 compatible = "regulator-fixed";
993 regulator-name = "+V1.8_AVDD_HDMI_PLL";
994 regulator-min-microvolt = <1800000>;
995 regulator-max-microvolt = <1800000>;
996 enable-active-high;
998 vin-supply = <®_1v8_vio>;
1001 reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {
1002 compatible = "regulator-fixed";
1003 regulator-name = "+V3.3_AVDD_HDMI";
1004 regulator-min-microvolt = <3300000>;
1005 regulator-max-microvolt = <3300000>;
1006 enable-active-high;
1008 vin-supply = <®_module_3v3>;
1011 reg_5v0_charge_pump: regulator-5v0-charge-pump {
1012 compatible = "regulator-fixed";
1013 regulator-name = "+V5.0";
1014 regulator-min-microvolt = <5000000>;
1015 regulator-max-microvolt = <5000000>;
1016 regulator-always-on;
1019 reg_lan_v_bus: regulator-lan-v-bus {
1020 compatible = "regulator-fixed";
1021 regulator-name = "LAN_V_BUS";
1022 regulator-min-microvolt = <5000000>;
1023 regulator-max-microvolt = <5000000>;
1024 enable-active-high;
1028 reg_module_3v3: regulator-module-3v3 {
1029 compatible = "regulator-fixed";
1030 regulator-name = "+V3.3";
1031 regulator-min-microvolt = <3300000>;
1032 regulator-max-microvolt = <3300000>;
1033 regulator-always-on;
1036 reg_module_3v3_audio: regulator-module-3v3-audio {
1037 compatible = "regulator-fixed";
1038 regulator-name = "+V3.3_AUDIO_AVDD_S";
1039 regulator-min-microvolt = <3300000>;
1040 regulator-max-microvolt = <3300000>;
1041 regulator-always-on;
1045 compatible = "toradex,tegra-audio-sgtl5000-colibri_t30",
1046 "nvidia,tegra-audio-sgtl5000";
1048 nvidia,audio-routing =
1052 nvidia,i2s-controller = <&tegra_i2s2>;
1053 nvidia,audio-codec = <&sgtl5000>;
1057 clock-names = "pll_a", "pll_a_out0", "mclk";
1059 assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
1062 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,