Lines Matching +full:1 +full:c23800
50 #address-cells = <1>;
51 #size-cells = <1>;
59 #address-cells = <1>;
60 #size-cells = <1>;
110 #address-cells = <1>;
161 #address-cells = <1>;
162 #size-cells = <1>;
192 #address-cells = <1>;
193 #size-cells = <1>;
208 #address-cells = <1>;
209 #size-cells = <1>;
212 system-control@1c00000 {
215 #address-cells = <1>;
216 #size-cells = <1>;
222 #address-cells = <1>;
223 #size-cells = <1>;
236 #address-cells = <1>;
237 #size-cells = <1>;
247 sram_c: sram@1d00000 {
250 #address-cells = <1>;
251 #size-cells = <1>;
261 dma: dma-controller@1c02000 {
269 nfc: nand-controller@1c03000 {
278 #address-cells = <1>;
282 spi0: spi@1c05000 {
292 #address-cells = <1>;
296 spi1: spi@1c06000 {
308 #address-cells = <1>;
312 emac: ethernet@1c0b000 {
317 allwinner,sram = <&emac_sram 1>;
323 mdio: mdio@1c0b080 {
327 #address-cells = <1>;
331 tcon0: lcd-controller@1c0c000 {
348 #address-cells = <1>;
352 #address-cells = <1>;
361 tcon0_in_be1: endpoint@1 {
362 reg = <1>;
367 tcon0_out: port@1 {
368 #address-cells = <1>;
370 reg = <1>;
372 tcon0_out_hdmi: endpoint@1 {
373 reg = <1>;
375 allwinner,tcon-channel = <1>;
381 tcon1: lcd-controller@1c0d000 {
398 #address-cells = <1>;
402 #address-cells = <1>;
411 tcon1_in_be1: endpoint@1 {
412 reg = <1>;
417 tcon1_out: port@1 {
418 #address-cells = <1>;
420 reg = <1>;
422 tcon1_out_hdmi: endpoint@1 {
423 reg = <1>;
425 allwinner,tcon-channel = <1>;
431 video-codec@1c0e000 {
439 allwinner,sram = <&ve_sram 1>;
442 mmc0: mmc@1c0f000 {
451 #address-cells = <1>;
455 mmc1: mmc@1c10000 {
462 #address-cells = <1>;
466 mmc2: mmc@1c11000 {
473 #address-cells = <1>;
477 mmc3: mmc@1c12000 {
484 #address-cells = <1>;
488 usb_otg: usb@1c13000 {
497 allwinner,sram = <&otg_sram 1>;
502 usbphy: phy@1c13400 {
503 #phy-cells = <1>;
516 ehci0: usb@1c14000 {
521 phys = <&usbphy 1>;
526 ohci0: usb@1c14400 {
531 phys = <&usbphy 1>;
536 crypto: crypto-engine@1c15000 {
544 hdmi: hdmi@1c16000 {
551 clock-names = "ahb", "mod", "pll-0", "pll-1";
559 #address-cells = <1>;
563 #address-cells = <1>;
572 hdmi_in_tcon1: endpoint@1 {
573 reg = <1>;
578 hdmi_out: port@1 {
579 reg = <1>;
584 spi2: spi@1c17000 {
594 #address-cells = <1>;
598 ahci: sata@1c18000 {
606 ehci1: usb@1c1c000 {
616 ohci1: usb@1c1c400 {
626 csi1: csi@1c1d000 {
636 spi3: spi@1c1f000 {
646 #address-cells = <1>;
650 ccu: clock@1c20000 {
655 #clock-cells = <1>;
656 #reset-cells = <1>;
659 intc: interrupt-controller@1c20400 {
663 #interrupt-cells = <1>;
666 pio: pinctrl@1c20800 {
841 timer@1c20c00 {
853 wdt: watchdog@1c20c90 {
860 rtc: rtc@1c20d00 {
866 pwm: pwm@1c20e00 {
874 spdif: spdif@1c21000 {
887 ir0: ir@1c21800 {
896 ir1: ir@1c21c00 {
905 i2s0: i2s@1c22400 {
918 lradc: lradc@1c22800 {
925 codec: codec@1c22c00 {
938 sid: eeprom@1c23800 {
943 rtp: rtp@1c25000 {
950 uart0: serial@1c28000 {
953 interrupts = <1>;
960 uart1: serial@1c28400 {
970 uart2: serial@1c28800 {
980 uart3: serial@1c28c00 {
990 uart4: serial@1c29000 {
1000 uart5: serial@1c29400 {
1010 uart6: serial@1c29800 {
1020 uart7: serial@1c29c00 {
1030 ps20: ps2@1c2a000 {
1038 ps21: ps2@1c2a400 {
1046 i2c0: i2c@1c2ac00 {
1054 #address-cells = <1>;
1058 i2c1: i2c@1c2b000 {
1066 #address-cells = <1>;
1070 i2c2: i2c@1c2b400 {
1078 #address-cells = <1>;
1082 can0: can@1c2bc00 {
1090 mali: gpu@1c40000 {
1111 fe0: display-frontend@1e00000 {
1122 #address-cells = <1>;
1125 fe0_out: port@1 {
1126 #address-cells = <1>;
1128 reg = <1>;
1135 fe0_out_be1: endpoint@1 {
1136 reg = <1>;
1143 fe1: display-frontend@1e20000 {
1154 #address-cells = <1>;
1157 fe1_out: port@1 {
1158 #address-cells = <1>;
1160 reg = <1>;
1167 fe1_out_be1: endpoint@1 {
1168 reg = <1>;
1175 be1: display-backend@1e40000 {
1186 #address-cells = <1>;
1190 #address-cells = <1>;
1199 be1_in_fe1: endpoint@1 {
1200 reg = <1>;
1205 be1_out: port@1 {
1206 #address-cells = <1>;
1208 reg = <1>;
1215 be1_out_tcon1: endpoint@1 {
1216 reg = <1>;
1223 be0: display-backend@1e60000 {
1234 #address-cells = <1>;
1238 #address-cells = <1>;
1247 be0_in_fe1: endpoint@1 {
1248 reg = <1>;
1253 be0_out: port@1 {
1254 #address-cells = <1>;
1256 reg = <1>;
1263 be0_out_tcon1: endpoint@1 {
1264 reg = <1>;