Lines Matching +full:0 +full:xfe000000
18 #size-cells = <0>;
19 cpu@0 {
22 reg = <0>;
44 ranges = <0xfe000000 0xfe000000 0x02000000
45 0x000f0000 0x000f0000 0x00010000>;
50 #clock-cells = <0>;
55 #clock-cells = <0>;
61 #clock-cells = <0>;
69 reg = <0xff10601c 0x4>;
79 reg = <0xfe002000 0x20>;
89 reg = <0xff100000 0x100>;
98 reg = <0xfe100000 0x1058>;
107 reg = <0xfe000000 0x400>;
111 dma-requests = <0>;
114 chan_allocation_order = <0>;
116 block_size = <0x7ff>;
125 #size-cells = <0>;
127 reg = <0xff120000 0x1000>;
134 #size-cells = <0>;
136 reg = <0xff121000 0x1000>;
143 #size-cells = <0>;
145 reg = <0xff122000 0x1000>;
152 #size-cells = <0>;
154 reg = <0xff123000 0x1000>;
161 #size-cells = <0>;
163 reg = <0xff124000 0x1000>;
171 #size-cells = <0>;
172 cell-index = <0>;
175 reg = <0xfe010000 0x20>;
182 #size-cells = <0>;
186 reg = <0xfe011000 0x20>;
194 reg = <0xff316000 0x400>;
198 global-packet-delay = <0x21>;
199 port-packet-delay = <0>;
203 reg = <0xfff00000 0x200>,
204 <0x000f0000 0x10000>,
205 <0xfff00200 0x105>,
206 <0xff10600c 0x1>,
207 <0xfe001018 0x1>;
219 reg = <0xff300000 0x7000>;
224 reg = <0xff307000 0x7000>;
228 reg = <0xff30e000 0x4000>;
233 reg = <0xff312000 0x4000>;
238 reg = <0xff319000 0x1000>;