Lines Matching +full:rk3399 +full:- +full:cru
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/rockchip,rk3399-dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip RK3399 SuperSpeed DWC3 USB SoC controller
10 - Heiko Stuebner <heiko@sntech.de>
14 const: rockchip,rk3399-dwc3
16 '#address-cells':
19 '#size-cells':
26 - description:
28 - description:
30 - description:
33 - description:
35 - description:
37 - description:
40 clock-names:
42 - const: ref_clk
43 - const: suspend_clk
44 - const: bus_clk
45 - const: aclk_usb3_rksoc_axi_perf
46 - const: aclk_usb3
47 - const: grf_clk
52 reset-names:
53 const: usb3-otg
62 - compatible
63 - '#address-cells'
64 - '#size-cells'
65 - ranges
66 - clocks
67 - clock-names
68 - resets
69 - reset-names
72 - |
73 #include <dt-bindings/clock/rk3399-cru.h>
74 #include <dt-bindings/power/rk3399-power.h>
75 #include <dt-bindings/interrupt-controller/arm-gic.h>
78 #address-cells = <2>;
79 #size-cells = <2>;
82 compatible = "rockchip,rk3399-dwc3";
83 #address-cells = <2>;
84 #size-cells = <2>;
86 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
87 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
88 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
89 clock-names = "ref_clk", "suspend_clk",
92 resets = <&cru SRST_A_USB3_OTG0>;
93 reset-names = "usb3-otg";
99 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>,
100 <&cru SCLK_USB3OTG0_SUSPEND>;
101 clock-names = "ref", "bus_early", "suspend";
104 phy-names = "usb2-phy", "usb3-phy";
107 snps,dis-u2-freeclk-exists-quirk;
109 snps,dis-del-phy-power-chg-quirk;
110 snps,dis-tx-ipgap-linecheck-quirk;
111 power-domains = <&power RK3399_PD_USB3>;