Lines Matching +full:dual +full:- +full:link
6 - compatible: Should contain "qcom,ehci-host"
7 - regs: offset and length of the register set in the memory map
8 - usb-phy: phandle for the PHY device
13 compatible = "qcom,ehci-host";
15 usb-phy = <&usb_otg>;
21 - compatible: Should contain:
22 "qcom,usb-otg-ci" for chipsets with ChipIdea 45nm PHY
23 "qcom,usb-otg-snps" for chipsets with Synopsys 28nm PHY
25 - regs: Offset and length of the register set in the memory map
26 - interrupts: interrupt-specifier for the OTG interrupt.
28 - clocks: A list of phandle + clock-specifier pairs for the
29 clocks listed in clock-names
30 - clock-names: Should contain the following:
37 - vdccx-supply: phandle to the regulator for the vdd supply for
39 - v1p8-supply: phandle to the regulator for the 1.8V supply
40 - v3p3-supply: phandle to the regulator for the 3.3V supply
42 - resets: A list of phandle + reset-specifier pairs for the
43 resets listed in reset-names
44 - reset-names: Should contain the following:
46 "link" USB LINK controller reset
48 - qcom,otg-control: OTG control (VBUS and ID notifications) can be one of
49 1 - PHY control
50 2 - PMIC control
53 - dr_mode: One of "host", "peripheral" or "otg". Defaults to "otg"
55 - switch-gpio: A phandle + gpio-specifier pair. Some boards are using Dual
57 D+/D- USB lines between connectors.
59 - qcom,phy-init-sequence: PHY configuration sequence values. This is related to Device
61 written is ULPI_EXT_VENDOR_SPECIFIC. Value of -1 is reserved as
63 For example: qcom,phy-init-sequence = < -1 0x63 >;
66 - qcom,phy-num: Select number of pyco-phy to use, can be one of
67 0 - PHY one, default
68 1 - Second PHY
72 - qcom,vdd-levels: This property must be a list of three integer values
76 - qcom,manual-pullup: If present, vbus is not routed to USB controller/phy
77 and controller driver therefore enables pull-up explicitly
80 - extcon: phandles to external connector devices. First phandle
83 device, which provide "USB-HOST" cable events. If one of
90 compatible = "qcom,usb-otg-snps";
98 clock-names = "phy", "core", "iface";
100 vddcx-supply = <&pm8841_s2_corner>;
101 v1p8-supply = <&pm8941_l6>;
102 v3p3-supply = <&pm8941_l24>;
105 reset-names = "phy", "link";
107 qcom,otg-control = <1>;
108 qcom,phy-init-sequence = < -1 0x63 >;
109 qcom,vdd-levels = <1 5 7>;