Lines Matching +full:tegra20 +full:- +full:usb +full:- +full:phy
1 * USB2 ChipIdea USB controller for ci13xxx
4 - compatible: should be one of:
5 "fsl,imx23-usb"
6 "fsl,imx27-usb"
7 "fsl,imx28-usb"
8 "fsl,imx6q-usb"
9 "fsl,imx6sl-usb"
10 "fsl,imx6sx-usb"
11 "fsl,imx6ul-usb"
12 "fsl,imx7d-usb"
13 "fsl,imx7ulp-usb"
14 "fsl,imx8mm-usb"
15 "lsi,zevio-usb"
16 "qcom,ci-hdrc"
18 "xlnx,zynq-usb-2.20a"
19 "nvidia,tegra20-udc"
20 "nvidia,tegra30-udc"
21 "nvidia,tegra114-udc"
22 "nvidia,tegra124-udc"
23 - reg: base address and length of the registers
24 - interrupts: interrupt for the USB controller
27 - phy_type: the type of the phy connected to the core. Should be one
30 - dr_mode: One of "host", "peripheral" or "otg". Defaults to "otg"
33 - usb-phy: phandle for the PHY device. Use "phys" instead.
34 - fsl,usbphy: phandle of usb phy that connects to the port. Use "phys" instead.
37 - clocks: reference to the USB clock
38 - phys: reference to the USB PHY
39 - phy-names: should be "usb-phy"
40 - vbus-supply: reference to the VBUS regulator
41 - maximum-speed: limit the maximum connection speed to "full-speed".
42 - tpl-support: TPL (Targeted Peripheral List) feature for targeted hosts
43 - itc-setting: interrupt threshold control register control, the setting
45 - ahb-burst-config: it is vendor dependent, the required value should be
50 - tx-burst-size-dword: it is vendor dependent, the tx burst size in dword
52 in 32-bit words while moving data from system memory to the USB
54 "ahb-burst-config" is set to 0, if this property is missing the reset
56 - rx-burst-size-dword: it is vendor dependent, the rx burst size in dword
58 in 32-bit words while moving data from the USB bus to system memory,
60 "ahb-burst-config" is set to 0, if this property is missing the reset
62 - extcon: phandles to external connector devices. First phandle should point to
63 external connector, which provide "USB" cable events, the second should point
64 to external connector device, which provide "USB-HOST" cable events. If one
67 - phy-clkgate-delay-us: the delay time (us) between putting the PHY into
68 low power mode and gating the PHY clock.
69 - non-zero-ttctrl-ttha: after setting this property, the value of register
85 - mux-controls: The mux control for toggling host/device output of this
88 - mux-control-names: Shall be "usb_switch" if mux-controls is specified.
89 - pinctrl-names: Names for optional pin modes in "default", "host", "device".
90 In case of HSIC-mode, "idle" and "active" pin modes are mandatory. In this
93 - pinctrl-n: alternate pin modes
96 - fsl,usbmisc: phandler of non-core register device, with one
97 argument that indicate usb controller index
98 - disable-over-current: disable over current detect
99 - over-current-active-low: over current signal polarity is active low.
100 - over-current-active-high: over current signal polarity is active high.
102 - power-active-high: power signal polarity is active high
103 - external-vbus-divider: enables off-chip resistor divider for Vbus
104 - samsung,picophy-pre-emp-curr-control: HS Transmitter Pre-Emphasis Current
106 USB_OTG*_DP and USB_OTG*_DN pins after a J-to-K or K-to-J transition.
109 - samsung,picophy-dc-vol-level-adjust: HS DC Voltage Level Adjustment.
110 Adjust the high-speed transmitter DC level voltage.
116 usb@f7ed0000 {
122 phy-names = "usb-phy";
123 vbus-supply = <®_usb0_vbus>;
124 itc-setting = <0x4>; /* 4 micro-frames */
126 ahb-burst-config = <0x0>;
127 tx-burst-size-dword = <0x10>; /* 64 bytes */
128 rx-burst-size-dword = <0x10>;
130 phy-clkgate-delay-us = <400>;
131 mux-controls = <&usb_switch>;
132 mux-control-names = "usb_switch";
137 usb@2184400 {
138 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
146 ahb-burst-config = <0x0>;
147 tx-burst-size-dword = <0x10>;
148 rx-burst-size-dword = <0x10>;
149 pinctrl-names = "idle", "active";
150 pinctrl-0 = <&pinctrl_usbh2_idle>;
151 pinctrl-1 = <&pinctrl_usbh2_active>;
152 #address-cells = <1>;
153 #size-cells = <0>;