Lines Matching +full:ck +full:- +full:gpios

4 - compatible: should be one of the following.
5     - mediatek,mt2701-spi: for mt2701 platforms
6     - mediatek,mt2712-spi: for mt2712 platforms
7     - mediatek,mt6589-spi: for mt6589 platforms
8     - mediatek,mt6765-spi: for mt6765 platforms
9     - mediatek,mt7622-spi: for mt7622 platforms
10     - "mediatek,mt7629-spi", "mediatek,mt7622-spi": for mt7629 platforms
11     - mediatek,mt8135-spi: for mt8135 platforms
12     - mediatek,mt8173-spi: for mt8173 platforms
13     - mediatek,mt8183-spi: for mt8183 platforms
14     - mediatek,mt6893-spi: for mt6893 platforms
15     - "mediatek,mt8192-spi", "mediatek,mt6765-spi": for mt8192 platforms
16     - "mediatek,mt8195-spi", "mediatek,mt6765-spi": for mt8195 platforms
17     - "mediatek,mt8516-spi", "mediatek,mt2712-spi": for mt8516 platforms
18     - "mediatek,mt6779-spi", "mediatek,mt6765-spi": for mt6779 platforms
20 - #address-cells: should be 1.
22 - #size-cells: should be 0.
24 - reg: Address and length of the register set for the device
26 - interrupts: Should contain spi interrupt
28 - clocks: phandles to input clocks.
30    -  <&clk26m>: specify parent clock 26MHZ.
31    -  <&topckgen CLK_TOP_SYSPLL3_D2>: specify parent clock 109MHZ.
33    -  <&topckgen CLK_TOP_SYSPLL4_D2>: specify parent clock 78MHZ.
34    -  <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ.
35    -  <&topckgen CLK_TOP_UNIVPLL1_D8>: specify parent clock 78MHZ.
39 - clock-names: shall be "parent-clk" for the parent clock, "sel-clk" for the
40   muxes clock, and "spi-clk" for the clock gate.
43 -cs-gpios: see spi-bus.txt.
45 - mediatek,pad-select: specify which pins group(ck/mi/mo/cs) spi
55 - SoC Specific Portion:
57 	compatible = "mediatek,mt8173-spi";
58 	#address-cells = <1>;
59 	#size-cells = <0>;
65 	clock-names = "parent-clk", "sel-clk", "spi-clk";
66 	cs-gpios = <&pio 105 GPIO_ACTIVE_LOW>, <&pio 72 GPIO_ACTIVE_LOW>;
67 	mediatek,pad-select = <1>, <0>;