Lines Matching +full:qspi +full:- +full:ocp
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vaishnav Achath <vaishnav.a@ti.com>
13 - $ref: spi-controller.yaml#
14 - if:
18 const: xlnx,versal-ospi-1.0
21 - power-domains
22 - if:
26 const: starfive,jh7110-qspi
33 reset-names:
37 enum: [ qspi, qspi-ocp, rstc_ref ]
44 reset-names:
48 enum: [ qspi, qspi-ocp ]
49 - if:
53 const: amd,pensando-elba-qspi
56 cdns,fifo-depth:
61 cdns,fifo-depth:
68 - items:
69 - enum:
70 - amd,pensando-elba-qspi
71 - ti,k2g-qspi
72 - ti,am654-ospi
73 - intel,lgm-qspi
74 - xlnx,versal-ospi-1.0
75 - intel,socfpga-qspi
76 - starfive,jh7110-qspi
77 - const: cdns,qspi-nor
78 - const: cdns,qspi-nor
82 - description: the controller register set
83 - description: the controller data area
92 clock-names:
94 - items:
95 - const: ref
96 - items:
97 - const: ref
98 - const: ahb
99 - const: apb
101 cdns,fifo-depth:
106 cdns,fifo-width:
112 cdns,trigger-address:
115 32-bit indirect AHB trigger address.
117 cdns,is-decoded-cs:
123 cdns,rclk-en:
126 Flag to indicate that QSPI return clock is used to latch the read
127 data rather than the QSPI clock. Make sure that QSPI return clock
130 power-domains:
137 reset-names:
141 enum: [ qspi, qspi-ocp, rstc_ref ]
144 - compatible
145 - reg
146 - interrupts
147 - clocks
148 - cdns,fifo-depth
149 - cdns,fifo-width
150 - cdns,trigger-address
151 - '#address-cells'
152 - '#size-cells'
157 - |
158 qspi: spi@ff705000 {
159 compatible = "cdns,qspi-nor";
160 #address-cells = <1>;
161 #size-cells = <0>;
166 cdns,fifo-depth = <128>;
167 cdns,fifo-width = <4>;
168 cdns,trigger-address = <0x00000000>;
170 reset-names = "qspi", "qspi-ocp";
173 compatible = "jedec,spi-nor";