Lines Matching +full:48 +full:khz

18   In order to support 48KHz and 44.1KHz family of sampling rates the parent
19   clock for AUDIO_REFCLK2 needs to be changed between PLL4 (for 48KHz) and
20   PLL15 (for 44.1KHz). The same PLLs are used for McASP10's AUXCLK clock via
24     48KHz family:
28     44.1KHz family:
33     48KHz family:
85             - description: Parent for CPB_McASP auxclk (for 48KHz)
86             - description: Parent for CPB_McASP auxclk (for 44.1KHz)
88             - description: Parent for CPB_SCKI clock (for 48KHz)
89             - description: Parent for CPB_SCKI clock (for 44.1KHz)
111             - description: Parent for CPB_McASP auxclk (for 48KHz)
113             - description: Parent for CPB_SCKI clock (for 48KHz)