Lines Matching +full:cache +full:- +full:controller +full:- +full:0
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/riscv/sifive-l2-cache.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive L2 Cache Controller
11 - Sagar Kadam <sagar.kadam@sifive.com>
12 - Paul Walmsley <paul.walmsley@sifive.com>
15 The SiFive Level 2 Cache Controller is used to provide access to fast copies
16 of memory for masters in a Core Complex. The Level 2 Cache Controller also
17 acts as directory-based coherency manager.
25 - sifive,fu540-c000-ccache
26 - sifive,fu740-c000-ccache
29 - compatible
34 - items:
35 - enum:
36 - sifive,fu540-c000-ccache
37 - sifive,fu740-c000-ccache
38 - const: cache
39 - items:
40 - const: microchip,mpfs-ccache
41 - const: sifive,fu540-c000-ccache
42 - const: cache
44 cache-block-size:
47 cache-level:
50 cache-sets:
53 cache-size:
56 cache-unified: true
61 - description: DirError interrupt
62 - description: DataError interrupt
63 - description: DataFail interrupt
64 - description: DirFail interrupt
69 next-level-cache: true
71 memory-region:
74 The reference to the reserved-memory for the L2 Loosely Integrated Memory region.
75 The reserved memory node should be defined as per the bindings in reserved-memory.txt.
78 - $ref: /schemas/cache-controller.yaml#
80 - if:
85 - sifive,fu740-c000-ccache
86 - microchip,mpfs-ccache
102 - if:
106 const: sifive,fu740-c000-ccache
110 cache-sets:
115 cache-sets:
121 - compatible
122 - cache-block-size
123 - cache-level
124 - cache-sets
125 - cache-size
126 - cache-unified
127 - interrupts
128 - reg
131 - |
132 cache-controller@2010000 {
133 compatible = "sifive,fu540-c000-ccache", "cache";
134 cache-block-size = <64>;
135 cache-level = <2>;
136 cache-sets = <1024>;
137 cache-size = <2097152>;
138 cache-unified;
139 reg = <0x2010000 0x1000>;
140 interrupt-parent = <&plic0>;
144 next-level-cache = <&L25>;
145 memory-region = <&l2_lim>;