Lines Matching +full:io +full:- +full:multiplex

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rzn1-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
11   - Geert Uytterhoeven <geert+renesas@glider.be>
16       - enum:
17           - renesas,r9a06g032-pinctrl # RZ/N1D
18           - renesas,r9a06g033-pinctrl # RZ/N1S
19       - const: renesas,rzn1-pinctrl   # Generic RZ/N1
23       - description: GPIO Multiplexing Level1 Register Block
24       - description: GPIO Multiplexing Level2 Register Block
29   clock-names:
35   - $ref: pinctrl.yaml#
38   - compatible
39   - reg
40   - clocks
41   - clock-names
45     - type: object
47         - $ref: pincfg-node.yaml#
48         - $ref: pinmux-node.yaml#
51         A pin multiplexing sub-node describes how to configure a set of (or a
53         A single sub-node may define several pin configurations.
70             <include/dt-bindings/pinctrl/rzn1-pinctrl.h>
71             These identifiers collapse the IO Multiplex Configuration Level 1
77         bias-disable: true
78         bias-pull-up:
80         bias-pull-down:
82         bias-high-impedance: true
83         drive-strength:
87         - pinmux
92     - type: object
97   - |
98     #include <dt-bindings/clock/r9a06g032-sysctrl.h>
99     #include <dt-bindings/pinctrl/rzn1-pinctrl.h>
101             compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl";
104             clock-names = "bus";
118              * Set the pull-up on the RXD pin of the UART.
125                             bias-pull-up;