Lines Matching +full:rmii +full:- +full:refclk +full:- +full:in
2 -----------------------------------------------
5 two 10/100/1000 Ethernet ports with selectable G/MII, RMII, and RGMII interfaces.
7 (GMII_SEL) in the System Control Module chapter (SCM). GMII_SEL register(s) and
8 bit fields placement in SCM are different between SoCs while fields meaning
10 +--------------+
11 +-------------------------------+ |SCM |
12 | CPSW | | +---------+ |
13 | +--------------------------------+gmii_sel | |
14 | | | | +---------+ |
15 | +----v---+ +--------+ | +--------------+
16 | |Port 1..<--+-->GMII/MII<------->
18 | +--------+ | +--------+ |
20 | | +--------+ |
21 | | | RMII <------->
22 | +--> | |
23 | | +--------+ |
25 | | +--------+ |
26 | | | RGMII <------->
27 | +--> | |
28 | +--------+ |
29 +-------------------------------+
36 PHY bindings (See phy/phy-bindings.txt).
39 - compatible : Should be "ti,am3352-phy-gmii-sel" for am335x platform
40 "ti,dra7xx-phy-gmii-sel" for dra7xx/am57xx platform
41 "ti,am43xx-phy-gmii-sel" for am43xx platform
42 "ti,dm814-phy-gmii-sel" for dm814x platform
43 "ti,am654-phy-gmii-sel" for AM654x/J721E platform
44 - reg : Address and length of the register set for the device
45 - #phy-cells : must be 2.
46 cell 1 - CPSW port number (starting from 1)
47 cell 2 - RMII refclk mode
50 phy_gmii_sel: phy-gmii-sel {
51 compatible = "ti,am3352-phy-gmii-sel";
53 #phy-cells = <2>;
57 compatible = "ti,am335x-cpsw","ti,cpsw";