Lines Matching +full:phy +full:- +full:am654 +full:- +full:serdes

1 TI AM654 SERDES
4  - compatible: Should be "ti,phy-am654-serdes"
5  - reg : Address and length of the register set for the device.
6  - #phy-cells: determine the number of cells that should be given in the
7 	phandle while referencing this phy. Should be "2". The 1st cell
8 	corresponds to the phy type (should be one of the types specified in
9 	include/dt-bindings/phy/phy.h) and the 2nd cell should be the serdes
12 		0 - USB3
13 		1 - PCIe0 Lane0
14 		2 - ICSS2 SGMII Lane0
16 		0 - PCIe1 Lane0
17 		1 - PCIe0 Lane1
18 		2 - ICSS2 SGMII Lane1
19  - power-domains: As documented by the generic PM domain bindings in
21  - clocks: List of clock-specifiers representing the input to the SERDES.
24  - clock-output-names: List of clock names for each of the clock outputs of
25 	SERDES. Should have 3 items for CMU reference clock,
27  - assigned-clocks: As defined in
28 	Documentation/devicetree/bindings/clock/clock-bindings.txt
29  - assigned-clock-parents: As defined in
30 	Documentation/devicetree/bindings/clock/clock-bindings.txt
31  - #clock-cells: Should be <1> to choose between the 3 output clocks.
32 	Defined in Documentation/devicetree/bindings/clock/clock-bindings.txt
34    The following macros are defined in dt-bindings/phy/phy-am654-serdes.h
36    specifying the clocks created by SERDES.
41  - mux-controls: Phandle to the multiplexer that is used to select the lane
42 	function. See #phy-cells above to see the multiplex values.
52 SERDES0 registers 3 clock outputs as indicated in clock-output-names. The
56 The assigned-clocks and assigned-clock-parents is used here to set the
60 serdes0: serdes@900000 {
61 	compatible = "ti,phy-am654-serdes";
63 	reg-names = "serdes";
64 	#phy-cells = <2>;
65 	power-domains = <&k3_pds 153>;
68 	clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk",
70 	assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
71 	assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>;
72 	ti,serdes-clk = <&serdes0_clk>;
73 	mux-controls = <&serdes_mux 0>;
74 	#clock-cells = <1>;
77 Example for PCIe consumer node using the SERDES PHY specifier is given below.
79         num-lanes = <2>;
81         phy-names = "pcie-phy0", "pcie-phy1";