Lines Matching +full:exynos +full:- +full:sataphy +full:- +full:i2c
1 Samsung S5P/Exynos SoC series MIPI CSIS/DSIM DPHY
2 -------------------------------------------------
5 - compatible : should be one of the listed compatibles:
6 - "samsung,s5pv210-mipi-video-phy"
7 - "samsung,exynos5420-mipi-video-phy"
8 - "samsung,exynos5433-mipi-video-phy"
9 - #phy-cells : from the generic phy bindings, must be 1;
12 - syscon - phandle to the PMU system controller
15 - samsung,pmu-syscon - phandle to the PMU system controller
16 - samsung,disp-sysreg - phandle to the DISP system registers controller
17 - samsung,cam0-sysreg - phandle to the CAM0 system registers controller
18 - samsung,cam1-sysreg - phandle to the CAM1 system registers controller
20 For "samsung,s5pv210-mipi-video-phy" compatible PHYs the second cell in
22 0 - MIPI CSIS 0,
23 1 - MIPI DSIM 0,
24 2 - MIPI CSIS 1,
25 3 - MIPI DSIM 1.
26 "samsung,exynos5420-mipi-video-phy" and "samsung,exynos5433-mipi-video-phy"
28 4 - MIPI CSIS 2.
30 Samsung Exynos SoC series Display Port PHY
31 -------------------------------------------------
34 - compatible : should be one of the following supported values:
35 - "samsung,exynos5250-dp-video-phy"
36 - "samsung,exynos5420-dp-video-phy"
37 - samsung,pmu-syscon: phandle for PMU system controller interface, used to
39 - #phy-cells : from the generic PHY bindings, must be 0;
41 Samsung S5P/Exynos SoC series USB PHY
42 -------------------------------------------------
45 - compatible : should be one of the listed compatibles:
46 - "samsung,exynos3250-usb2-phy"
47 - "samsung,exynos4210-usb2-phy"
48 - "samsung,exynos4x12-usb2-phy"
49 - "samsung,exynos5250-usb2-phy"
50 - "samsung,exynos5420-usb2-phy"
51 - "samsung,s5pv210-usb2-phy"
52 - reg : a list of registers used by phy driver
53 - first and obligatory is the location of phy modules registers
54 - samsung,sysreg-phandle - handle to syscon used to control the system registers
55 - samsung,pmureg-phandle - handle to syscon used to control PMU registers
56 - #phy-cells : from the generic phy bindings, must be 1;
57 - clocks and clock-names:
58 - the "phy" clock is required by the phy module, used as a gate
59 - the "ref" clock is used to get the rate of the clock provided to the
63 - vbus-supply: power-supply phandle for vbus power source
66 meaning is compatible dependent. For the currently supported SoCs (Exynos 4210
67 and Exynos 4212) it is as follows:
68 0 - USB device ("device"),
69 1 - USB host ("host"),
70 2 - HSIC0 ("hsic0"),
71 3 - HSIC1 ("hsic1"),
74 Exynos 4210 and Exynos 4212 use mode switching and require that mode switch
79 For Exynos 4412 (compatible with Exynos 4212):
82 compatible = "samsung,exynos4x12-usb2-phy";
85 clock-names = "phy", "ref";
86 #phy-cells = <1>;
87 samsung,sysreg-phandle = <&sys_reg>;
88 samsung,pmureg-phandle = <&pmu_reg>;
93 phy-consumer@12340000 {
95 phy-names = "phy";
102 ---------------------------
104 SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
108 - compatible : compatible list, contains "samsung,exynos5250-sata-phy"
109 - reg : offset and length of the SATA PHY register set;
110 - #phy-cells : must be zero
111 - clocks : must be exactly one entry
112 - clock-names : must be "sata_phyctrl"
113 - samsung,exynos-sataphy-i2c-phandle : a phandle to the I2C device, no arguments
114 - samsung,syscon-phandle : a phandle to the PMU system controller, no arguments
117 sata_phy: sata-phy@12170000 {
118 compatible = "samsung,exynos5250-sata-phy";
121 clock-names = "sata_phyctrl";
122 #phy-cells = <0>;
123 samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
124 samsung,syscon-phandle = <&pmu_syscon>;
127 Device-Tree bindings for sataphy i2c client driver
128 --------------------------------------------------
131 compatible: Should be "samsung,exynos-sataphy-i2c"
132 - reg: I2C address of the sataphy i2c device.
136 sata_phy_i2c:sata-phy@38 {
137 compatible = "samsung,exynos-sataphy-i2c";
142 --------------------------------------------------
145 - compatible : Should be set to one of the following supported values:
146 - "samsung,exynos5250-usbdrd-phy" - for exynos5250 SoC,
147 - "samsung,exynos5420-usbdrd-phy" - for exynos5420 SoC.
148 - "samsung,exynos5433-usbdrd-phy" - for exynos5433 SoC.
149 - "samsung,exynos7-usbdrd-phy" - for exynos7 SoC.
150 - reg : Register offset and length of USB DRD PHY register set;
151 - clocks: Clock IDs array as required by the controller
152 - clock-names: names of clocks correseponding to IDs in the clock property;
154 - phy: main PHY clock (same as USB DRD controller i.e. DWC3 IP clock),
156 - ref: PHY's reference clock (usually crystal clock), used for
160 - optional clocks: Exynos5433 & Exynos7 SoC has now following additional
162 - phy_pipe: for PIPE3 phy
163 - phy_utmi: for UTMI+ phy
164 - itp: for ITP generation
165 - samsung,pmu-syscon: phandle for PMU system controller interface, used to
167 - #phy-cells : from the generic PHY bindings, must be 1;
169 For "samsung,exynos5250-usbdrd-phy" and "samsung,exynos5420-usbdrd-phy"
172 0 - UTMI+ type phy,
173 1 - PIPE3 type phy,
177 compatible = "samsung,exynos5250-usbdrd-phy";
180 clock-names = "phy", "ref";
181 samsung,pmu-syscon = <&pmu_system_controller>;
182 #phy-cells = <1>;
185 - aliases: For SoCs like Exynos5420 having multiple USB 3.0 DRD PHY controllers,
195 Samsung Exynos SoC series PCIe PHY controller
196 --------------------------------------------------
198 - compatible : Should be set to "samsung,exynos5440-pcie-phy"
199 - #phy-cells : Must be zero
200 - reg : a register used by phy driver.
201 - First is for phy register, second is for block register.
202 - reg-names : Must be set to "phy" and "block".
205 pcie_phy0: pcie-phy@270000 {
206 #phy-cells = <0>;
207 compatible = "samsung,exynos5440-pcie-phy";
209 reg-names = "phy", "block";