Lines Matching +full:ch0 +full:- +full:2
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/samsung,ufs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alim Akhtar <alim.akhtar@samsung.com>
13 "#phy-cells":
18 - samsung,exynos7-ufs-phy
19 - samsung,exynosautov9-ufs-phy
20 - tesla,fsd-ufs-phy
25 reg-names:
27 - const: phy-pma
33 clock-names:
37 samsung,pmu-syscon:
38 $ref: /schemas/types.yaml#/definitions/phandle-array
43 - description: phandle for PMU system controller interface, used to
44 control pmu registers bits for ufs m-phy
45 - description: offset of the pmu control register
51 - "#phy-cells"
52 - compatible
53 - reg
54 - reg-names
55 - clocks
56 - clock-names
57 - samsung,pmu-syscon
60 - if:
64 const: samsung,exynos7-ufs-phy
70 - description: PLL reference clock
71 - description: symbol clock for input symbol (rx0-ch0 symbol clock)
72 - description: symbol clock for input symbol (rx1-ch1 symbol clock)
73 - description: symbol clock for output symbol (tx0 symbol clock)
75 clock-names:
77 - const: ref_clk
78 - const: rx1_symbol_clk
79 - const: rx0_symbol_clk
80 - const: tx0_symbol_clk
86 - description: PLL reference clock
88 clock-names:
90 - const: ref_clk
95 - |
96 #include <dt-bindings/clock/exynos7-clk.h>
98 ufs_phy: ufs-phy@15571800 {
99 compatible = "samsung,exynos7-ufs-phy";
101 reg-names = "phy-pma";
102 samsung,pmu-syscon = <&pmu_system_controller>;
103 #phy-cells = <0>;
108 clock-names = "ref_clk", "rx1_symbol_clk",