Lines Matching +full:memory +full:- +full:mapped
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
16 # Please create a separate DT-schema for your DWC PCIe Endpoint controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie-ep
23 - compatible
26 - $ref: /schemas/pci/pci-ep.yaml#
27 - $ref: /schemas/pci/snps,dw-pcie-common.yaml#
32 DBI, DBI2 reg-spaces and outbound memory window are required for the
33 normal controller functioning. iATU memory IO region is also required
34 if the space is unrolled (IP-core version >= 4.80a).
38 reg-names:
43 - description:
44 Basic DWC PCIe controller configuration-space accessible over
45 the DBI interface. This memory space is either activated with
46 CDM/ELBI = 0 and CS2 = 0 or is a contiguous memory region
51 - description:
52 Shadow DWC PCIe config-space registers. This space is selected
54 the PCI-SIG PCIe CFG-space with the shadow registers for some
56 mainly relevant for the end-point controller configuration,
60 - description:
61 External Local Bus registers. It's an application-dependent
64 be accessed over some platform-specific means (for instance
67 - description:
69 unrolled memory space with the internal Address Translation
71 and CS2 = 1. For IP-core releases prior v4.80a, these registers
73 set of viewport CSRs mapped into the PL space. Note iATU is
74 normally mapped to the 0x0 address of this region, while eDMA
77 - description:
78 Platform-specific eDMA registers. Some platforms may have eDMA
79 CSRs mapped in a non-standard base address. The registers offset
80 can be changed or the MS/LS-bits of the address can be attached
81 in an additional RTL block before the MEM-IO transactions reach
84 - description:
86 PCS and PHY CSRs accessible over a dedicated memory mapped
89 platform-specific method.
91 - description:
92 Outbound iATU-capable memory-region which will be used to
93 generate various application-specific traffic on the PCIe bus
98 - description:
99 Vendor-specific CSR names. Consider using the generic names above
102 - description: See native 'elbi/app' CSR region for details.
104 - description: See native 'atu' CSR region for details.
107 - contains:
109 - contains:
115 but in addition to the native set the platforms may have a link- or
116 PM-related IRQs specified.
120 interrupt-names:
125 - description:
129 - description:
134 - description:
140 pattern: '^dma([0-9]|1[0-5])?$'
141 - description:
146 - description:
150 - description:
151 Application-specific IRQ raised depending on the vendor-specific
154 - description:
159 - description:
163 - description:
164 Vendor-specific IRQ names. Consider using the generic names above
167 - description: See native "app" IRQ for details
170 max-functions:
174 - compatible
175 - reg
176 - reg-names
181 - |
182 pcie-ep@dfd00000 {
183 compatible = "snps,dw-pcie-ep";
187 reg-names = "dbi", "dbi2", "addr_space";
190 interrupt-names = "dma0", "dma1";
193 clock-names = "dbi", "ref";
196 reset-names = "dbi", "phy";
199 phy-names = "pcie0", "pcie1", "pcie2", "pcie3";
201 max-link-speed = <3>;
202 max-functions = /bits/ 8 <4>;