Lines Matching +full:mem +full:- +full:base

4 - compatible: Should contain "rockchip,rk3399-pcie-ep"
5 - reg: Two register ranges as listed in the reg-names property
6 - reg-names: Must include the following names
7 	- "apb-base"
8 	- "mem-base"
9 - clocks: Must contain an entry for each entry in clock-names.
10 		See ../clocks/clock-bindings.txt for details.
11 - clock-names: Must include the following entries:
12 	- "aclk"
13 	- "aclk-perf"
14 	- "hclk"
15 	- "pm"
16 - resets: Must contain seven entries for each entry in reset-names.
18 - reset-names: Must include the following names
19 	- "core"
20 	- "mgmt"
21 	- "mgmt-sticky"
22 	- "pipe"
23 	- "pm"
24 	- "aclk"
25 	- "pclk"
26 - pinctrl-names : The pin control state names
27 - pinctrl-0: The "default" pinctrl state
28 - phys: Must contain an phandle to a PHY for each entry in phy-names.
29 - phy-names: Must include 4 entries for all 4 lanes even if some of
30   them won't be used for your cases. Entries are of the form "pcie-phy-N":
32   (see example below and you MUST also refer to ../phy/rockchip-pcie-phy.txt
33   for changing the #phy-cells of phy node to support it)
34 - rockchip,max-outbound-regions: Maximum number of outbound regions
37 - num-lanes: number of lanes to use
38 - max-functions: Maximum number of functions that can be configured (default 1).
40 pcie0-ep: pcie@f8000000 {
41 	compatible = "rockchip,rk3399-pcie-ep";
42 	#address-cells = <3>;
43 	#size-cells = <2>;
44 	rockchip,max-outbound-regions = <16>;
47 	clock-names = "aclk", "aclk-perf",
49 	max-functions = /bits/ 8 <8>;
50 	num-lanes = <4>;
52 	reg-names = "apb-base", "mem-base";
56 	reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
59 	phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3";
60 	pinctrl-names = "default";
61 	pinctrl-0 = <&pcie_clkreq>;