Lines Matching +full:syscon +full:- +full:phy +full:- +full:mode
6 Documentation/devicetree/bindings/pci/designware-pcie.txt
8 Please refer to Documentation/devicetree/bindings/pci/designware-pcie.txt
12 Required Properties:-
14 compatibility: Should be "ti,keystone-pcie" for RC on Keystone2 SoC
15 Should be "ti,am654-pcie-rc" for RC on AM654x SoC
16 reg: Three register ranges as listed in the reg-names property
17 reg-names: "dbics" for the DesignWare PCIe registers, "app" for the
22 interrupt-cells: should be set to 1
24 (required if the compatible is "ti,keystone-pcie")
25 msi-map: As specified in Documentation/devicetree/bindings/pci/pci-msi.txt
26 (required if the compatible is "ti,am654-pcie-rc".
28 ti,syscon-pcie-id : phandle to the device control module required to set device
30 ti,syscon-pcie-mode : phandle to the device control module required to configure
31 PCI in either RC mode or EP mode.
34 pcie_msi_intc: msi-interrupt-controller {
35 interrupt-controller;
36 #interrupt-cells = <1>;
37 interrupt-parent = <&gic>;
49 interrupt-cells: should be set to 1
52 pcie_intc: legacy-interrupt-controller {
53 interrupt-controller;
54 #interrupt-cells = <1>;
55 interrupt-parent = <&gic>;
62 Optional properties:-
63 phys: phandle to generic Keystone SerDes PHY for PCI
64 phy-names: name of the generic Keystone SerDes PHY for PCI
65 - If boot loader already does PCI link establishment, then phys and
66 phy-names shouldn't be present.
71 1. pcie_bus clock-names not used. Instead, a phandle to phys is used.
76 Required Properties:-
78 compatibility: Should be "ti,am654-pcie-ep" for EP on AM654x SoC
79 reg: Four register ranges as listed in the reg-names property
80 reg-names: "dbics" for the DesignWare PCIe registers, "app" for the
84 num-ib-windows: As specified in
85 Documentation/devicetree/bindings/pci/designware-pcie.txt
86 num-ob-windows: As specified in
87 Documentation/devicetree/bindings/pci/designware-pcie.txt
88 num-lanes: As specified in
89 Documentation/devicetree/bindings/pci/designware-pcie.txt
90 power-domains: As documented by the generic PM domain bindings in
92 ti,syscon-pcie-mode: phandle to the device control module required to configure
93 PCI in either RC mode or EP mode.
95 Optional properties:-
97 phys: list of PHY specifiers (used by generic PHY framework)
98 phy-names: must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
99 number of lanes as specified in *num-lanes* property.
100 ("phys" and "phy-names" DT bindings are specified in
101 Documentation/devicetree/bindings/phy/phy-bindings.txt)
104 pcie-ep {
105 compatible = "ti,am654-pcie-ep";
108 reg-names = "app", "dbics", "addr_space", "atu";
109 power-domains = <&k3_pds 120>;
110 ti,syscon-pcie-mode = <&pcie0_mode>;
111 num-lanes = <1>;
112 num-ib-windows = <16>;
113 num-ob-windows = <16>;