Lines Matching +full:syscon +full:- +full:phy +full:- +full:mode

10 - compatible: Should be
11 		"mediatek,mt2701-eth": for MT2701 SoC
12 		"mediatek,mt7623-eth", "mediatek,mt2701-eth": for MT7623 SoC
13 		"mediatek,mt7622-eth": for MT7622 SoC
14 		"mediatek,mt7629-eth": for MT7629 SoC
15 		"ralink,rt5350-eth": for Ralink Rt5350F and MT7628/88 SoC
16 - reg: Address and length of the register set for the device
17 - interrupts: Should contain the three frame engines interrupts in numeric
19 - clocks: the clock used by the core
20 - clock-names: the names of the clock listed in the clocks property. These are
28 - power-domains: phandle to the power domain that the ethernet is part of
29 - resets: Should contain phandles to the ethsys reset signals
30 - reset-names: Should contain the names of reset signal listed in the resets
33 - mediatek,ethsys: phandle to the syscon node that handles the port setup
34 - mediatek,infracfg: phandle to the syscon node that handles the path from
35 	GMAC to PHY variants, which is required for MT7629 SoC.
36 - mediatek,sgmiisys: a list of phandles to the syscon node that handles the
41 - mediatek,pctl: phandle to the syscon node that handles the ports slew rate
47 - compatible: Should be "mediatek,eth-mac"
48 - reg: The number of the MAC
49 - phy-handle: see ethernet.txt file in the same directory and
50 	the phy-mode "trgmii" required being provided when reg
51 	is equal to 0 and the MAC uses fixed-link to connect
57 	compatible = "mediatek,mt7623-eth";
63 	clock-names = "ethif", "esw", "gp2", "gp1";
67 	power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
69 	reset-names = "eth";
72 	#address-cells = <1>;
73 	#size-cells = <0>;
76 		compatible = "mediatek,eth-mac";
78 		phy-handle = <&phy0>;
82 		compatible = "mediatek,eth-mac";
84 		phy-handle = <&phy1>;
87 	mdio-bus {
88 		phy0: ethernet-phy@0 {
90 			phy-mode = "rgmii";
93 		phy1: ethernet-phy@1 {
95 			phy-mode = "rgmii";