Lines Matching +full:mt7986 +full:- +full:wed +full:- +full:pcie
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Bianconi <lorenzo@kernel.org>
11 - Felix Fietkau <nbd@nbd.name>
20 - mediatek,mt2701-eth
21 - mediatek,mt7623-eth
22 - mediatek,mt7621-eth
23 - mediatek,mt7622-eth
24 - mediatek,mt7629-eth
25 - mediatek,mt7981-eth
26 - mediatek,mt7986-eth
27 - mediatek,mt7988-eth
28 - ralink,rt5350-eth
34 clock-names: true
40 power-domains:
46 reset-names:
48 - const: fe
49 - const: gmac
50 - const: ppe
57 cci-control-port: true
72 $ref: /schemas/types.yaml#/definitions/phandle-array
81 mediatek,wed:
82 $ref: /schemas/types.yaml#/definitions/phandle-array
90 mediatek,wed-pcie:
93 Phandle to the mediatek wed-pcie controller.
95 dma-coherent: true
97 mdio-bus:
101 "#address-cells":
104 "#size-cells":
108 - $ref: ethernet-controller.yaml#
109 - if:
114 - mediatek,mt2701-eth
115 - mediatek,mt7623-eth
125 clock-names:
127 - const: ethif
128 - const: esw
129 - const: gp1
130 - const: gp2
140 mediatek,wed: false
142 mediatek,wed-pcie: false
144 - if:
149 - mediatek,mt7621-eth
159 clock-names:
161 - const: ethif
162 - const: fe
166 mediatek,wed: false
168 mediatek,wed-pcie: false
170 - if:
174 const: mediatek,mt7622-eth
184 clock-names:
186 - const: ethif
187 - const: esw
188 - const: gp0
189 - const: gp1
190 - const: gp2
191 - const: sgmii_tx250m
192 - const: sgmii_rx250m
193 - const: sgmii_cdr_ref
194 - const: sgmii_cdr_fb
195 - const: sgmii_ck
196 - const: eth2pll
204 mediatek,pcie-mirror:
207 Phandle to the mediatek pcie-mirror controller.
209 mediatek,wed-pcie: false
211 - if:
215 const: mediatek,mt7629-eth
225 clock-names:
227 - const: ethif
228 - const: sgmiitop
229 - const: esw
230 - const: gp0
231 - const: gp1
232 - const: gp2
233 - const: fe
234 - const: sgmii_tx250m
235 - const: sgmii_rx250m
236 - const: sgmii_cdr_ref
237 - const: sgmii_cdr_fb
238 - const: sgmii2_tx250m
239 - const: sgmii2_rx250m
240 - const: sgmii2_cdr_ref
241 - const: sgmii2_cdr_fb
242 - const: sgmii_ck
243 - const: eth2pll
249 mediatek,wed: false
251 mediatek,wed-pcie: false
253 - if:
257 const: mediatek,mt7981-eth
267 clock-names:
269 - const: fe
270 - const: gp2
271 - const: gp1
272 - const: wocpu0
273 - const: sgmii_ck
274 - const: sgmii_tx250m
275 - const: sgmii_rx250m
276 - const: sgmii_cdr_ref
277 - const: sgmii_cdr_fb
278 - const: sgmii2_tx250m
279 - const: sgmii2_rx250m
280 - const: sgmii2_cdr_ref
281 - const: sgmii2_cdr_fb
282 - const: netsys0
283 - const: netsys1
291 - if:
295 const: mediatek,mt7986-eth
305 clock-names:
307 - const: fe
308 - const: gp2
309 - const: gp1
310 - const: wocpu1
311 - const: wocpu0
312 - const: sgmii_tx250m
313 - const: sgmii_rx250m
314 - const: sgmii_cdr_ref
315 - const: sgmii_cdr_fb
316 - const: sgmii2_tx250m
317 - const: sgmii2_rx250m
318 - const: sgmii2_cdr_ref
319 - const: sgmii2_cdr_fb
320 - const: netsys0
321 - const: netsys1
329 - if:
333 const: mediatek,mt7988-eth
343 clock-names:
345 - const: crypto
346 - const: fe
347 - const: gp2
348 - const: gp1
349 - const: gp3
350 - const: ethwarp_wocpu2
351 - const: ethwarp_wocpu1
352 - const: ethwarp_wocpu0
353 - const: esw
354 - const: netsys0
355 - const: netsys1
356 - const: sgmii_tx250m
357 - const: sgmii_rx250m
358 - const: sgmii2_tx250m
359 - const: sgmii2_rx250m
360 - const: top_usxgmii0_sel
361 - const: top_usxgmii1_sel
362 - const: top_sgm0_sel
363 - const: top_sgm1_sel
364 - const: top_xfi_phy0_xtal_sel
365 - const: top_xfi_phy1_xtal_sel
366 - const: top_eth_gmii_sel
367 - const: top_eth_refck_50m_sel
368 - const: top_eth_sys_200m_sel
369 - const: top_eth_sys_sel
370 - const: top_eth_xgmii_sel
371 - const: top_eth_mii_sel
372 - const: top_netsys_sel
373 - const: top_netsys_500m_sel
374 - const: top_netsys_pao_2x_sel
375 - const: top_netsys_sync_250m_sel
376 - const: top_netsys_ppefb_250m_sel
377 - const: top_netsys_warp_sel
378 - const: wocpu1
379 - const: wocpu0
380 - const: xgp1
381 - const: xgp2
382 - const: xgp3
389 "^mac@[0-1]$":
393 - $ref: ethernet-controller.yaml#
398 const: mediatek,eth-mac
404 - reg
405 - compatible
408 - compatible
409 - reg
410 - interrupts
411 - clocks
412 - clock-names
413 - mediatek,ethsys
418 - |
419 #include <dt-bindings/interrupt-controller/arm-gic.h>
420 #include <dt-bindings/interrupt-controller/irq.h>
421 #include <dt-bindings/clock/mt7622-clk.h>
422 #include <dt-bindings/power/mt7622-power.h>
425 #address-cells = <2>;
426 #size-cells = <2>;
429 compatible = "mediatek,mt7622-eth";
445 clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
449 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
452 cci-control-port = <&cci_control2>;
453 mediatek,pcie-mirror = <&pcie_mirror>;
455 dma-coherent;
457 #address-cells = <1>;
458 #size-cells = <0>;
460 mdio0: mdio-bus {
461 #address-cells = <1>;
462 #size-cells = <0>;
464 phy0: ethernet-phy@0 {
468 phy1: ethernet-phy@1 {
474 compatible = "mediatek,eth-mac";
475 phy-mode = "rgmii";
476 phy-handle = <&phy0>;
481 compatible = "mediatek,eth-mac";
482 phy-mode = "rgmii";
483 phy-handle = <&phy1>;
489 - |
490 #include <dt-bindings/interrupt-controller/arm-gic.h>
491 #include <dt-bindings/interrupt-controller/irq.h>
492 #include <dt-bindings/clock/mt7622-clk.h>
495 #address-cells = <2>;
496 #size-cells = <2>;
509 compatible = "mediatek,mt7986-eth";
530 clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
538 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
540 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
543 #address-cells = <1>;
544 #size-cells = <0>;
546 mdio: mdio-bus {
547 #address-cells = <1>;
548 #size-cells = <0>;
550 phy5: ethernet-phy@0 {
551 compatible = "ethernet-phy-id67c9.de0a";
552 phy-mode = "2500base-x";
553 reset-gpios = <&pio 6 1>;
554 reset-deassert-us = <20000>;
558 phy6: ethernet-phy@1 {
559 compatible = "ethernet-phy-id67c9.de0a";
560 phy-mode = "2500base-x";
566 compatible = "mediatek,eth-mac";
567 phy-mode = "2500base-x";
568 phy-handle = <&phy5>;
573 compatible = "mediatek,eth-mac";
574 phy-mode = "2500base-x";
575 phy-handle = <&phy6>;